Commit 9c129bc5 authored by Konstantin Luebeck's avatar Konstantin Luebeck

Fixed spelling mistakes.

parent b1948b13
......@@ -17,11 +17,11 @@ This part is pretty straight forward. You can look up how to setup a new Vivado
[https://github.com/k0nze/zedboard_axi4_master_burst_example#creating-a-new-vivado-project](https://github.com/k0nze/zedboard_axi4_master_burst_example#creating-a-new-vivado-project)
Thoughout this tutorial the name for the Vivado project is `pl_to_ps_interrupt_example`.
Throughout this tutorial the name for the Vivado project is `pl_to_ps_interrupt_example`.
## Creating a Custom AXI4 IP
After you successfully created a new Vivado project do the following steps to create a custom AXI IP which will issue the interrupts from the PL to the PS with an AXI slave interface.
After you successfully created a new Vivado project carry out the following steps to create a custom AXI IP which will issue the interrupts from the PL to the PS with an AXI4-Lite slave interface.
1. Open: _Menu -> Tools -> Create and Package IP_.
......@@ -55,7 +55,7 @@ After you successfully created a new Vivado project do the following steps to cr
## Edit AXI4 IP
After the successful creation of the new IP a new Vivado project was opened. In this project you can find the Vivado generated Verilog code for the AXI4-Lite slave and a top module (wrapper) which contains the AXI4-Lite slave.
After the successful creation of the new AXI4 IP a new Vivado project was opened. In this project you can find the Vivado generated Verilog code for the AXI4-Lite slave and a top module (wrapper) which contains the AXI4-Lite slave.
![sources](./images/edit_ip01.png "sources")
......@@ -99,7 +99,7 @@ axi4_pl_interrupt_generator_v1_0_S00_AXI # (
.interrupt_1(interrupt_1),
```
`interrupt_0`and `interrupt_1` will be connected to `interrupt_0` and `interrupt_1` of the top module. To add `interrupt_0` and `interrupt_1` to the top module navigate to `// Users to add ports here` and add the following:
`interrupt_0` and `interrupt_1` will be connected to `interrupt_0` and `interrupt_1` of the top module. To add `interrupt_0` and `interrupt_1` to the top module navigate to `// Users to add ports here` and add the following:
```verilog
// Users to add ports here
......@@ -168,7 +168,7 @@ So that your custom AXI4 IP can be implemented on the Zynq PL and connected to t
![create block diagram](./images/block_diagram01.png "create block diagram")
2. Choose a name, directory, and specify a source set for the block diagram. In this tutorial everything stays at the default.
2. Choose a name, directory, and specify a source set for the block diagram. In this tutorial everything stays at its default.
![block diagram choose name](./images/block_diagram02.png "block diagram choose name")
......@@ -221,7 +221,7 @@ So that your custom AXI4 IP can be implemented on the Zynq PL and connected to t
![block diagram run connection automation](./images/block_diagram11.png "block diagram connection automation")
13. Check _S00\_AXI_ in the tree on the left-hand side. Select _/processing\_system7\_0/FCLK\ CLK0_ in the list of _Clock Connections_ and click on OK.
13. Check _S00\_AXI_ in the tree on the left-hand side. Select _/processing\_system7\_0/FCLK\_CLK0_ in the list of _Clock Connections_ and click on OK.
![block diagram clock connection](./images/block_diagram12.png "block diagram clock connection")
......@@ -241,7 +241,7 @@ So that your custom AXI4 IP can be implemented on the Zynq PL and connected to t
![block diagram draw connection](./images/block_diagram16.png "block diagram connection")
17. Afterwards connection the _dout_ output of the _xlconcat\_0_ to the _IRQ\_F2P_ input of the Zynq PS.
17. Afterwards connect the _dout_ output of the _xlconcat\_0_ to the _IRQ\_F2P_ input of the Zynq PS.
![block diagram zynq ps interrupt connection](./images/block_diagram17.png "block diagram zynq ps interrupt connection")
......@@ -309,7 +309,7 @@ Make sure your Zedboard is turned on. If the green _POWER_ led is on the Zedboar
![zedboard led](./images/zedboard02.jpg "zedboard led")
The C program which will be transferred to the Zynq PS will initiate an AXI4 read/write burst transaction over the AXI4-Lite slave interface of your custom AXI4 IP and afterwards it will verify the result.
The C program which will be transferred to the Zynq PS is going to setup the interrupt system of the Zynq PS and enables the interrupts for the `IRQ_F2P[1:0]` ports for a rising edge. When the interrupt system is enabled the interrupts will be generated by writing a `1` into `slv_reg0[0:0]` and `slv_reg1[0:0]`. This will trigger the interrupt service routines `isr0` and `isr1` which will clear the interrupts by writing a `0` to `slv_reg0[0:0]` or `slv_reg1[0:0]`. Then the interrupt for `IRQ_F2P[1:1]` will be disabled and by writing a `1` into `slv_reg0[0:0]` and `slv_reg1[0:0]` new interrupts will be generated. This will only trigger the interrupt service routine `isr0` since the interrupt `IRQ_F2P[1:1]` is disabled.
1. You have to export the hardware configuration to the Xilinx SDK. Go to _Menu -> File -> Export -> Export Hardware ..._.
......@@ -339,7 +339,7 @@ The C program which will be transferred to the Zynq PS will initiate an AXI4 rea
![hello world](./images/software06.png "hello world")
7. After the project was successfully created open `helloworld.c` under _Project Explorer -> _axi4\_pl\_interrupt\_generator\_test -> src -> helloworld.c_
7. After the project was successfully created open `helloworld.c` under _Project Explorer -> axi4\_pl\_interrupt\_generator\_test -> src -> helloworld.c_
![helloworld.c](./images/software07.png "helloworld.c")
......@@ -365,18 +365,11 @@ The C program which will be transferred to the Zynq PS will initiate an AXI4 rea
int setup_interrupt_system();
void isr0 (void *InstancePtr);
void isr1 (void *InstancePtr);
void isr0 (void *intc_inst_ptr);
void isr1 (void *intc_inst_ptr);
void nops(unsigned int num);
void nops(unsigned int num) {
int i;
for(i = 0; i < num; i++) {
asm("nop");
}
}
int main()
{
int main() {
init_platform();
xil_printf("== START ==\n\r");
......@@ -442,13 +435,13 @@ The C program which will be transferred to the Zynq PS will initiate an AXI4 rea
}
// interrupt service routine for IRQ_F2P[0:0]
void isr0 (void *InstancePtr) {
void isr0 (void *intc_inst_ptr) {
xil_printf("isr0 called\n\r");
*(baseaddr_p+0) = 0x00000000;
}
// interrupt service routine for IRQ_F2P[1:1]
void isr1 (void *InstancePtr) {
void isr1 (void *intc_inst_ptr) {
xil_printf("isr1 called\n\r");
*(baseaddr_p+1) = 0x00000000;
}
......@@ -509,6 +502,13 @@ The C program which will be transferred to the Zynq PS will initiate an AXI4 rea
return XST_SUCCESS;
}
void nops(unsigned int num) {
int i;
for(i = 0; i < num; i++) {
asm("nop");
}
}
```
9. Program the Zynq PL with the previously generated bitstream by going to _Menu -> Xilinx Tools -> Program FPGA_.
......
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