Commit b589c8a8 authored by Konstantin Luebeck's avatar Konstantin Luebeck

Added sources, scripts, and updated README.

parent 9ad136c5
*.wdb
*.jou
xsim.dir
*.pb
*.log
# HDL Simulation with Vivado XSIM (command line)
[`and_tb_xsim_rtl.sh`](./and_tb_xsim_rtl.sh) contains the commands which have to be executed before a HDL simulation and the command to start the HDL simulation with Vivado XSIM.
[`and_tb_xsim_rtl.tcl`](./and_tb_xsim_rtl.tcl) contains commands for the XSIM simulation.
## Run simulation
```bash
./and_tb_xsim_rtl.sh
```
`timescale 1ns/1ps
module AND(
a,
b,
x
);
input wire a;
input wire b;
output wire x;
assign x = a & b;
endmodule
`timescale 1ns/1ps
module AND_tb();
reg a;
reg b;
wire x;
initial begin
a = 0;
b = 0;
#1
$display("x %b", x);
#9
a = 1;
b = 0;
$display("x %b", x);
a = 0;
b = 1;
#1
$display("x %b", x);
#9
a = 1;
b = 1;
#1
$display("x %b", x);
#9
a = 0;
b = 0;
end
AND DUT(
.a(a),
.b(b),
.x(x)
);
endmodule
#!/bin/bash
xvlog and.v
xvlog and_tb.v
xelab -debug typical AND_tb -s tb
xsim tb -t and_tb_xsim_rtl.tcl
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