Commit dbb5df04 authored by Christoph Gerum's avatar Christoph Gerum

Add missing configuration script

parent 1d2249de
import m5
from m5.objects import *
import argparse
import sys
parser = argparse.ArgumentParser(description='Simulate benchmark')
# parser.add_argument('--type', help='CPU Type (one of: o3, minor, timing)')
parser.add_argument('-c', help='binary to execute')
args = parser.parse_args()
CPU = DerivO3CPU
# width of pipeline configuration
width = 1
CPU.decodeWidth = width # std: 8
CPU.commitWidth = width
CPU.fetchWidth = width
CPU.issueWidth = width
CPU.renameWidth = width
CPU.squashWidth = width
# CPU.wbWidth = width if (width > 8) else 8
CPU.fetchQueueSize = width
# functional unit configuration
CPU.fuPool.FUList[0].count = 6 # IntALU
CPU.fuPool.FUList[1].count = 2 # IntMultDiv
CPU.fuPool.FUList[2].count = 4 # FP_ALU
CPU.fuPool.FUList[3].count = 2 # FP_MultDiv
CPU.fuPool.FUList[4].count = 0 # ReadPort
CPU.fuPool.FUList[5].count = 4 # SIMD_Unit
CPU.fuPool.FUList[6].count = 0 # WritePort
CPU.fuPool.FUList[7].count = 4 # RdWrPort
CPU.fuPool.FUList[8].count = 1 # IprPort
class L1Cache(BaseCache):
assoc = 2
hit_latency = 2
response_latency = 2
mshrs = 2
size = '4kB'
tgts_per_mshr = 20
is_top_level = True
system = System()
system.clk_domain = SrcClockDomain()
system.clk_domain.clock = '2GHz'
system.clk_domain.voltage_domain = VoltageDomain()
system.mem_mode = 'timing'
system.mem_ranges = [AddrRange('512MB')]
system.cpu = CPU()
system.cpu.createInterruptController()
system.membus = SystemXBar()
system.icache = L1Cache()
system.dcache = L1Cache()
system.cpu.icache_port = system.icache.cpu_side
system.cpu.dcache_port = system.dcache.cpu_side
system.dcache.mem_side = system.membus.slave
system.icache.mem_side = system.membus.slave
system.system_port = system.membus.slave
#system.mem_ctrl = DDR3_1600_x64()
system.mem_ctrl = DDR4_2400_x64()
system.mem_ctrl.range = system.mem_ranges[0]
system.mem_ctrl.port = system.membus.master
process = LiveProcess()
process.cmd = [args.c]
system.cpu.workload = process
system.cpu.createThreads()
root = Root(full_system = False, system = system)
m5.instantiate()
print "Beginning simulation!"
exit_event = m5.simulate()
print 'Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause())
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