Add templates for further exercises

aufgaben/blatt01/run_bench.py

+import m5
+from m5.objects import *
+import argparse
+import sys
+
+parser = argparse.ArgumentParser(description='Simulate benchmark')
+parser.add_argument('--type', help='CPU Type (one of: o3, minor, timing)')
+parser.add_argument('--benchmark', 
+                    help='Benchmark to execute')
+args = parser.parse_args()
+
+
+if args.type == 'o3':
+    CPU = DerivO3CPU
+elif args.type == 'minor':
+    CPU = MinorCPU
+elif args.type == 'timing':
+    CPU = TimingSimpleCPU
+else:
+    print "Could not find cpu type: ", args.type
+    sys.exit(-1)
+
+
+class L1Cache(BaseCache):
+    assoc = 2
+    hit_latency = 2
+    response_latency = 2
+    mshrs = 2
+    size = '4kB'
+    tgts_per_mshr = 20
+    is_top_level = True
+
+
+system = System()
+
+system.clk_domain = SrcClockDomain()
+system.clk_domain.clock = '2GHz'	
+system.clk_domain.voltage_domain = VoltageDomain()
+
+system.mem_mode = 'timing'
+system.mem_ranges = [AddrRange('512MB')]
+
+system.cpu = CPU()
+system.cpu.createInterruptController()
+
+system.membus = SystemXBar()
+
+system.icache = L1Cache()
+system.dcache = L1Cache()
+
+system.cpu.icache_port = system.icache.cpu_side
+system.cpu.dcache_port = system.dcache.cpu_side
+
+system.dcache.mem_side  = system.membus.slave
+system.icache.mem_side  = system.membus.slave
+
+
+
+system.system_port = system.membus.slave
+
+#system.mem_ctrl = DDR3_1600_x64()
+system.mem_ctrl = DDR4_2400_x64()
+system.mem_ctrl.range = system.mem_ranges[0]
+system.mem_ctrl.port = system.membus.master
+
+
+process = LiveProcess()
+process.cmd = [args.benchmark]
+system.cpu.workload = process
+system.cpu.createThreads()
+
+root = Root(full_system = False, system = system)
+
+m5.instantiate()
+
+print "Beginning simulation!"
+
+exit_event = m5.simulate()
+
+print 'Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause())
+

aufgaben/blatt02/blatt02.md

 Title: Blatt 2
 status: hidden
 
-# Superskalare Architekturen 
+# Superskalare Architekturen (**DRAFT**)
 
 ## Aufgabe 1
 

aufgaben/blatt03/blatt03.md

+Title: Blatt 3
+status: hidden
+
+# Spekulative Ausführung (**DRAFT**)
+

aufgaben/blatt04/blatt04.md

+Title: Blatt 4
+status: hidden
+
+# Multicore Architekturen (**DRAFT**)
+

aufgaben/blatt05/blatt05.md

+Title: Blatt 5
+status: hidden
+
+# Spekulative Ausführung (**DRAFT**)
+

aufgaben/blatt06/blatt06.md

+Title: Blatt 6
+status: hidden
+
+# Spekulative Ausführung (**DRAFT**)
+