Commit ac492513 authored by Christoph Gerum's avatar Christoph Gerum

Add correct MCConfig

parent c28ddd7f
import m5
from m5.objects import *
import argparse
import sys
import shlex
from m5.util import addToPath
addToPath('/home/vagrant/parallel_computer_architecture/gem5/configs/common')
# import Options
parser = argparse.ArgumentParser(description='Simulate')
parser.add_argument('-c', help='binary to execute')
parser.add_argument('-o', help='The options to pass to the binary, use " " around the entire string')
parser.add_argument('-w', help='width of pipeline')
parser.add_argument('-n', help='Number of CPUs')
parser.add_argument('--cpu-type', help='CPU Type (one of: o3, timing)')
args = parser.parse_args()
class L1Cache(BaseCache):
assoc = 2
hit_latency = 2
response_latency = 2
mshrs = 2
size = '4kB'
tgts_per_mshr = 20
is_top_level = True
system = System()
system.clk_domain = SrcClockDomain()
system.clk_domain.clock = '2GHz'
system.clk_domain.voltage_domain = VoltageDomain()
system.mem_mode = 'timing'
system.mem_ranges = [AddrRange('512MB')]
system.membus = SystemXBar()
################################################################################
num_cpus = int(args.n) if args.n else 2
if args.cpu_type and args.cpu_type == "timing":
system.cpu = [TimingSimpleCPU(cpu_id=idx) for idx in xrange(num_cpus)]
else:
system.cpu = [DerivO3CPU(cpu_id=idx) for idx in xrange(num_cpus)]
if args.cpu_type != "timing":
for CPU in system.cpu:
# width of pipeline configuration
width = 8 if args.w is None else args.w
CPU.decodeWidth = width # std: 8
CPU.commitWidth = width
CPU.fetchWidth = width
CPU.issueWidth = width
CPU.renameWidth = width
CPU.squashWidth = width
# CPU.wbWidth = width if (width > 8) else 8
CPU.fetchQueueSize = width
system.icache = [L1Cache() for i in xrange(num_cpus)]
system.dcache = [L1Cache() for i in xrange(num_cpus)]
for cpuid in xrange(num_cpus):
system.cpu[cpuid].createInterruptController()
system.cpu[cpuid].icache_port = system.icache[cpuid].cpu_side
system.cpu[cpuid].dcache_port = system.dcache[cpuid].cpu_side
system.dcache[cpuid].mem_side = system.membus.slave
system.icache[cpuid].mem_side = system.membus.slave
system.system_port = system.membus.slave
system.mem_ctrl = DDR4_2400_x64(device_size='32MB')
system.mem_ctrl.range = system.mem_ranges[0]
system.mem_ctrl.port = system.membus.master
process = LiveProcess()
process.cmd = shlex.split(args.c)
if args.o:
process.cmd += shlex.split(args.o)
for cpuid in xrange(num_cpus):
system.cpu[cpuid].workload = process
system.cpu[cpuid].createThreads()
root = Root(full_system = False, system = system)
m5.instantiate()
print "Beginning simulation!"
exit_event = m5.simulate()
print 'Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause())
print "Cycles: ", m5.curTick()
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