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advanced_computer_architecture
exercises
Commits
39041235
Commit
39041235
authored
Apr 14, 2016
by
Christoph Gerum
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aufgaben/blatt01/configs/fs-copy-simplyfied.py
aufgaben/blatt01/configs/fs-copy-simplyfied.py
+0
-344
aufgaben/blatt01/configs/old/caches.py
aufgaben/blatt01/configs/old/caches.py
+0
-42
aufgaben/blatt01/configs/old/caches.pyc
aufgaben/blatt01/configs/old/caches.pyc
+0
-0
aufgaben/blatt01/configs/old/se-copy-simple.py
aufgaben/blatt01/configs/old/se-copy-simple.py
+0
-280
aufgaben/blatt01/configs/old/simple-caches.py
aufgaben/blatt01/configs/old/simple-caches.py
+0
-61
aufgaben/blatt01/configs/simple.py
aufgaben/blatt01/configs/simple.py
+0
-42
aufgaben/blatt01/configs/simple_change-cpu.py
aufgaben/blatt01/configs/simple_change-cpu.py
+0
-50
aufgaben/blatt01/configs/two_level_try.py
aufgaben/blatt01/configs/two_level_try.py
+0
-151
aufgaben/blatt01/exec/hello/hello_world
aufgaben/blatt01/exec/hello/hello_world
+0
-0
aufgaben/blatt01/exec/hello/hello_world.c
aufgaben/blatt01/exec/hello/hello_world.c
+0
-6
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aufgaben/blatt01/configs/fs-copy-simplyfied.py
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e7e1ce25
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aufgaben/blatt01/configs/old/caches.py
deleted
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e7e1ce25
from
m5.objects
import
BaseCache
class
L1Cache
(
BaseCache
):
assoc
=
2
hit_latency
=
2
response_latency
=
2
mshrs
=
4
tgts_per_mshr
=
20
# is_top_level = True
def
connectCPU
(
self
,
cpu
):
raise
NotImplementedError
def
connectBus
(
self
,
bus
):
self
.
mem_side
=
bus
.
slave
class
L1ICache
(
L1Cache
):
size
=
'16kB'
def
connectCPU
(
self
,
cpu
):
self
.
cpu_side
=
cpu
.
icache_port
class
L1DCache
(
L1Cache
):
size
=
'64kB'
def
connectCPU
(
self
,
cpu
):
self
.
cpu_side
=
spu
.
dcache_port
class
L2Cache
(
BaseCache
):
size
=
'256kB'
assoc
=
8
hit_latency
=
20
response_latency
=
20
mshrs
=
20
tgts_per_mshr
=
12
def
connectCPUSideBus
(
self
,
bus
):
self
.
cpu_side
=
bus
.
master
def
connectMemSideBus
(
self
,
bus
):
self
.
mem_side
=
bus
.
slave
aufgaben/blatt01/configs/old/caches.pyc
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File deleted
aufgaben/blatt01/configs/old/se-copy-simple.py
deleted
100644 → 0
View file @
e7e1ce25
# Copyright (c) 2012-2013 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Copyright (c) 2006-2008 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Steve Reinhardt
# Simple test script
#
# "m5 test.py"
import
optparse
import
sys
import
os
import
m5
from
m5.defines
import
buildEnv
from
m5.objects
import
*
from
m5.util
import
addToPath
,
fatal
addToPath
(
'../common'
)
addToPath
(
'../ruby'
)
import
Options
import
Ruby
import
Simulation
import
CacheConfig
import
CpuConfig
import
MemConfig
from
Caches
import
*
from
cpu2000
import
*
def
get_processes
(
options
):
"""Interprets provided options and returns a list of processes"""
multiprocesses
=
[]
inputs
=
[]
outputs
=
[]
errouts
=
[]
pargs
=
[]
workloads
=
options
.
cmd
.
split
(
';'
)
if
options
.
input
!=
""
:
inputs
=
options
.
input
.
split
(
';'
)
if
options
.
output
!=
""
:
outputs
=
options
.
output
.
split
(
';'
)
if
options
.
errout
!=
""
:
errouts
=
options
.
errout
.
split
(
';'
)
if
options
.
options
!=
""
:
pargs
=
options
.
options
.
split
(
';'
)
idx
=
0
for
wrkld
in
workloads
:
process
=
LiveProcess
()
process
.
executable
=
wrkld
process
.
cwd
=
os
.
getcwd
()
if
options
.
env
:
with
open
(
options
.
env
,
'r'
)
as
f
:
process
.
env
=
[
line
.
rstrip
()
for
line
in
f
]
if
len
(
pargs
)
>
idx
:
process
.
cmd
=
[
wrkld
]
+
pargs
[
idx
].
split
()
else
:
process
.
cmd
=
[
wrkld
]
if
len
(
inputs
)
>
idx
:
process
.
input
=
inputs
[
idx
]
if
len
(
outputs
)
>
idx
:
process
.
output
=
outputs
[
idx
]
if
len
(
errouts
)
>
idx
:
process
.
errout
=
errouts
[
idx
]
multiprocesses
.
append
(
process
)
idx
+=
1
if
options
.
smt
:
assert
(
options
.
cpu_type
==
"detailed"
)
return
multiprocesses
,
idx
else
:
return
multiprocesses
,
1
parser
=
optparse
.
OptionParser
()
Options
.
addCommonOptions
(
parser
)
Options
.
addSEOptions
(
parser
)
if
'--ruby'
in
sys
.
argv
:
Ruby
.
define_options
(
parser
)
(
options
,
args
)
=
parser
.
parse_args
()
if
args
:
print
"Error: script doesn't take any positional arguments"
sys
.
exit
(
1
)
multiprocesses
=
[]
numThreads
=
1
if
options
.
bench
:
apps
=
options
.
bench
.
split
(
"-"
)
if
len
(
apps
)
!=
options
.
num_cpus
:
print
"number of benchmarks not equal to set num_cpus!"
sys
.
exit
(
1
)
for
app
in
apps
:
try
:
if
buildEnv
[
'TARGET_ISA'
]
==
'alpha'
:
exec
(
"workload = %s('alpha', 'tru64', '%s')"
%
(
app
,
options
.
spec_input
))
elif
buildEnv
[
'TARGET_ISA'
]
==
'arm'
:
exec
(
"workload = %s('arm_%s', 'linux', '%s')"
%
(
app
,
options
.
arm_iset
,
options
.
spec_input
))
else
:
exec
(
"workload = %s(buildEnv['TARGET_ISA', 'linux', '%s')"
%
(
app
,
options
.
spec_input
))
multiprocesses
.
append
(
workload
.
makeLiveProcess
())
except
:
print
>>
sys
.
stderr
,
"Unable to find workload for %s: %s"
%
(
buildEnv
[
'TARGET_ISA'
],
app
)
sys
.
exit
(
1
)
elif
options
.
cmd
:
multiprocesses
,
numThreads
=
get_processes
(
options
)
else
:
print
>>
sys
.
stderr
,
"No workload specified. Exiting!
\n
"
sys
.
exit
(
1
)
(
CPUClass
,
test_mem_mode
,
FutureClass
)
=
Simulation
.
setCPUClass
(
options
)
CPUClass
.
numThreads
=
numThreads
# Check -- do not allow SMT with multiple CPUs
if
options
.
smt
and
options
.
num_cpus
>
1
:
fatal
(
"You cannot use SMT with multiple CPUs!"
)
np
=
options
.
num_cpus
system
=
System
(
cpu
=
[
CPUClass
(
cpu_id
=
i
)
for
i
in
xrange
(
np
)],
mem_mode
=
test_mem_mode
,
mem_ranges
=
[
AddrRange
(
options
.
mem_size
)],
cache_line_size
=
options
.
cacheline_size
)
if
numThreads
>
1
:
system
.
multi_thread
=
True
# Create a top-level voltage domain
system
.
voltage_domain
=
VoltageDomain
(
voltage
=
options
.
sys_voltage
)
# Create a source clock for the system and set the clock period
system
.
clk_domain
=
SrcClockDomain
(
clock
=
options
.
sys_clock
,
voltage_domain
=
system
.
voltage_domain
)
# Create a CPU voltage domain
system
.
cpu_voltage_domain
=
VoltageDomain
()
# Create a separate clock domain for the CPUs
system
.
cpu_clk_domain
=
SrcClockDomain
(
clock
=
options
.
cpu_clock
,
voltage_domain
=
system
.
cpu_voltage_domain
)
# If elastic tracing is enabled, then configure the cpu and attach the elastic
# trace probe
if
options
.
elastic_trace_en
:
CpuConfig
.
config_etrace
(
CPUClass
,
system
.
cpu
,
options
)
# All cpus belong to a common cpu_clk_domain, therefore running at a common
# frequency.
for
cpu
in
system
.
cpu
:
cpu
.
clk_domain
=
system
.
cpu_clk_domain
if
is_kvm_cpu
(
CPUClass
)
or
is_kvm_cpu
(
FutureClass
):
if
buildEnv
[
'TARGET_ISA'
]
==
'x86'
:
system
.
vm
=
KvmVM
()
for
process
in
multiprocesses
:
process
.
useArchPT
=
True
process
.
kvmInSE
=
True
else
:
fatal
(
"KvmCPU can only be used in SE mode with x86"
)
# Sanity check
if
options
.
fastmem
:
if
CPUClass
!=
AtomicSimpleCPU
:
fatal
(
"Fastmem can only be used with atomic CPU!"
)
if
(
options
.
caches
or
options
.
l2cache
):
fatal
(
"You cannot use fastmem in combination with caches!"
)
if
options
.
simpoint_profile
:
if
not
options
.
fastmem
:
# Atomic CPU checked with fastmem option already
fatal
(
"SimPoint generation should be done with atomic cpu and fastmem"
)
if
np
>
1
:
fatal
(
"SimPoint generation not supported with more than one CPUs"
)
for
i
in
xrange
(
np
):
if
options
.
smt
:
system
.
cpu
[
i
].
workload
=
multiprocesses
elif
len
(
multiprocesses
)
==
1
:
system
.
cpu
[
i
].
workload
=
multiprocesses
[
0
]
else
:
system
.
cpu
[
i
].
workload
=
multiprocesses
[
i
]
if
options
.
fastmem
:
system
.
cpu
[
i
].
fastmem
=
True
if
options
.
simpoint_profile
:
system
.
cpu
[
i
].
addSimPointProbe
(
options
.
simpoint_interval
)
if
options
.
checker
:
system
.
cpu
[
i
].
addCheckerCpu
()
system
.
cpu
[
i
].
createThreads
()
if
options
.
ruby
:
if
options
.
cpu_type
==
"atomic"
or
options
.
cpu_type
==
"AtomicSimpleCPU"
:
print
>>
sys
.
stderr
,
"Ruby does not work with atomic cpu!!"
sys
.
exit
(
1
)
Ruby
.
create_system
(
options
,
False
,
system
)
assert
(
options
.
num_cpus
==
len
(
system
.
ruby
.
_cpu_ports
))
system
.
ruby
.
clk_domain
=
SrcClockDomain
(
clock
=
options
.
ruby_clock
,
voltage_domain
=
system
.
voltage_domain
)
for
i
in
xrange
(
np
):
ruby_port
=
system
.
ruby
.
_cpu_ports
[
i
]
# Create the interrupt controller and connect its ports to Ruby
# Note that the interrupt controller is always present but only
# in x86 does it have message ports that need to be connected
system
.
cpu
[
i
].
createInterruptController
()
# Connect the cpu's cache ports to Ruby
system
.
cpu
[
i
].
icache_port
=
ruby_port
.
slave
system
.
cpu
[
i
].
dcache_port
=
ruby_port
.
slave
if
buildEnv
[
'TARGET_ISA'
]
==
'x86'
:
system
.
cpu
[
i
].
interrupts
[
0
].
pio
=
ruby_port
.
master
system
.
cpu
[
i
].
interrupts
[
0
].
int_master
=
ruby_port
.
slave
system
.
cpu
[
i
].
interrupts
[
0
].
int_slave
=
ruby_port
.
master
system
.
cpu
[
i
].
itb
.
walker
.
port
=
ruby_port
.
slave
system
.
cpu
[
i
].
dtb
.
walker
.
port
=
ruby_port
.
slave
else
:
MemClass
=
Simulation
.
setMemClass
(
options
)
system
.
membus
=
SystemXBar
()
system
.
system_port
=
system
.
membus
.
slave
CacheConfig
.
config_cache
(
options
,
system
)
MemConfig
.
config_mem
(
options
,
system
)
root
=
Root
(
full_system
=
False
,
system
=
system
)
Simulation
.
run
(
options
,
root
,
system
,
FutureClass
)
aufgaben/blatt01/configs/old/simple-caches.py
deleted
100644 → 0
View file @
e7e1ce25
import
m5
from
m5.objects
import
*
from
Caches
import
*
system
=
System
()
system
.
clk_domain
=
SrcClockDomain
(
clock
=
'1GHz'
,
voltage_domain
=
VoltageDomain
())
system
.
mem_mode
=
'timing'
system
.
mem_ranges
=
[
AddrRange
(
'512MB'
)]
system
.
cpu
=
TimingSimpleCPU
()
# system.cpu = MinorCPU()
# system.cpu = DerivO3CPU()
system
.
cpu
.
icache
=
L1ICache
()
system
.
cpu
.
dcache
=
L1DCache
()
system
.
cpu
.
icache
.
connectCPU
(
system
.
cpu
.
icache_port
)
system
.
cpu
.
dcache
.
connectCPU
(
system
.
cpu
.
dcache_port
)
system
.
l2bus
=
CoherentXBar
()
system
.
cpu
.
icache
.
connectBus
(
system
.
l2bus
)
system
.
cpu
.
dcache
.
connectBus
(
system
.
l2bus
)
system
.
l2cache
=
L2Cache
()
system
.
l2cache
.
connectCPUSideBus
(
system
.
l2bus
)
system
.
membus
=
SystemXBar
()
system
.
l2chace
.
connectMemSideBus
(
system
.
membus
)
# system.cpu.icache_port = system.membus.slave
# system.cpu.dcache_port = system.membus.slave
system
.
cpu
.
createInterruptController
()
system
.
system_port
=
system
.
membus
.
slave
system
.
mem_ctrl
=
DDR3_1600_x64
()
system
.
mem_ctrl
.
range
=
system
.
mem_ranges
[
0
]
system
.
mem_ctrl
.
port
=
system
.
membus
.
master
process
=
LiveProcess
()
process
.
cmd
=
[
'/home/vagrant/advanced_computer_architecture/exercises/blatt01/exec/hello/hello_world'
]
system
.
cpu
.
workload
=
process
system
.
cpu
.
createThreads
()
root
=
Root
(
full_system
=
False
,
system
=
system
)
m5
.
instantiate
()
exit_event
=
m5
.
simulate
()
# newprocess = LiveProcess()
# newprocess.cmd = ['/home/vagrant/advanced_computer_architecture/exercises/blatt01/exec/automotive/basicmath/basicmath_small']
# system.cpu.workload = newprocess
# system.cpu.createThreads()
# print "Beginning simulation!"
# exit_event = m5.simulate()
print
'Exiting @ tick %i because %s'
%
(
m5
.
curTick
(),
exit_event
.
getCause
())
aufgaben/blatt01/configs/simple.py
deleted
100644 → 0
View file @
e7e1ce25
import
m5
from
m5.objects
import
*
system
=
System
()
system
.
clk_domain
=
SrcClockDomain
(
clock
=
'1GHz'
,
voltage_domain
=
VoltageDomain
())
system
.
mem_mode
=
'timing'
system
.
mem_ranges
=
[
AddrRange
(
'512MB'
)]
# system.cpu = TimingSimpleCPU()
system
.
cpu
=
MinorCPU
()
# system.cpu = DerivO3CPU()
# TODO: Add Caches for working DerivO3CPU!
system
.
membus
=
SystemXBar
()
system
.
cpu
.
icache_port
=
system
.
membus
.
slave
system
.
cpu
.
dcache_port
=
system
.
membus
.
slave
system
.
cpu
.
createInterruptController
()
system
.
system_port
=
system
.
membus
.
slave
system
.
mem_ctrl
=
DDR3_1600_x64
()
system
.
mem_ctrl
.
range
=
system
.
mem_ranges
[
0
]
system
.
mem_ctrl
.
port
=
system
.
membus
.
master
process
=
LiveProcess
()
# process.cmd = ['/home/vagrant/advanced_computer_architecture/exercises/blatt01/exec/hello/hello_world']
process
.
cmd
=
[
'/home/vagrant/advanced_computer_architecture/exercises/blatt01/exec/automotive/basicmath/basicmath_small'
]
system
.
cpu
.
workload
=
process
system
.
cpu
.
createThreads
()
root
=
Root
(
full_system
=
False
,
system
=
system
)
m5
.
instantiate
()
print
"Beginning simulation!"
exit_event
=
m5
.
simulate
()
print
'Exiting @ tick %i because %s'
%
(
m5
.
curTick
(),
exit_event
.
getCause
())
aufgaben/blatt01/configs/simple_change-cpu.py
deleted
100644 → 0
View file @
e7e1ce25
import
m5
from
m5.objects
import
*
# TODO: Add Caches for working DerivO3CPU!
# system.cpu = TimingSimpleCPU()
# system.cpu = DerivO3CPU()
run_cpu
=
MinorCPU
()
run_cpu
.
createInterruptController
()
switch_cpu
=
TimingSimpleCPU
(
switched_out
=
True
)
switch_cpu
.
createInterruptController
()
switch_cpu
.
clk_domain
=
SrcClockDomain
(
clock
=
'1GHz'
,
voltage_domain
=
VoltageDomain
())
switch_cpu_list
=
[(
run_cpu
,
switch_cpu
)]
system
=
System
(
cpu
=
run_cpu
)
system
.
clk_domain
=
SrcClockDomain
(
clock
=
'1GHz'
,
voltage_domain
=
VoltageDomain
())
system
.
mem_mode
=
'timing'
system
.
mem_ranges
=
[
AddrRange
(
'512MB'
)]
system
.
membus
=
SystemXBar
()
system
.
cpu
.
icache_port
=
system
.
membus
.
slave
system
.
cpu
.
dcache_port
=
system
.
membus
.
slave
switch_cpu
.
icache_port
=
system
.
membus
.
slave
switch_cpu
.
dcache_port
=
system
.
membus
.
slave
system
.
system_port
=
system
.
membus
.
slave
system
.
mem_ctrl
=
DDR3_1600_x64
()
system
.
mem_ctrl
.
range
=
system
.
mem_ranges
[
0
]
system
.
mem_ctrl
.
port
=
system
.
membus
.
master
process
=
LiveProcess
(
cmd
=
'/home/vagrant/advanced_computer_architecture/exercises/blatt01/exec/automotive/basicmath/basicmath_small'
)
system
.
cpu
.
workload
=
process
system
.
cpu
.
createThreads
()
switch_cpu
.
workload
=
process
switch_cpu
.
createThreads
()
root
=
Root
(
full_system
=
False
,
system
=
system
,
switch_cpu
=
switch_cpu
)
#root = Root(full_system = False, system = system)
m5
.
instantiate
()
print
"Beginning simulation!"
exit_event
=
m5
.
simulate
(
10000
)
m5
.
switchCpus
(
system
,
switch_cpu_list
)
exit_event
=
m5
.
simulate
(
10000
)
m5
.
switchCpus
(
system
,
switch_cpu_list
)
print
'Exiting @ tick %i because %s'
%
(
m5
.
curTick
(),
exit_event
.
getCause
())
aufgaben/blatt01/configs/two_level_try.py
deleted
100644 → 0
View file @
e7e1ce25
# -*- coding: utf-8 -*-
# Copyright (c) 2015 Jason Power
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Jason Power
""" This file creates a single CPU and a two-level cache system.
This script takes a single parameter which specifies a binary to execute.
If none is provided it executes 'hello' by default (mostly used for testing)
See Part 1, Chapter 3: Adding cache to the configuration script in the
learning_gem5 book for more information about this script.
This file exports options for the L1 I/D and L2 cache sizes.
IMPORTANT: If you modify this file, it's likely that the Learning gem5 book
also needs to be updated. For now, email Jason <power.jg@gmail.com>
"""
# import the m5 (gem5) library created when gem5 is built
import
m5
# import all of the SimObjects
from
m5.objects
import
*
# Add the common scripts to our path
m5
.
util
.
addToPath
(
'../../common'
)
# import the caches which we made
from
caches
import
*
# import the SimpleOpts module
import
SimpleOpts
# Set the usage message to display
SimpleOpts
.
set_usage
(
"usage: %prog [options] <binary to execute>"
)
# Finalize the arguments and grab the opts so we can pass it on to our objects
(
opts
,
args
)
=
SimpleOpts
.
parse_args
()
# get ISA for the default binary to run. This is mostly for simple testing
isa
=
str
(
m5
.
defines
.
buildEnv
[
'TARGET_ISA'
]).
lower
()
# Default to running 'hello', use the compiled ISA to find the binary
binary
=
'tests/test-progs/hello/bin/'
+
isa
+
'/linux/hello'
# Check if there was a binary passed in via the command line and error if
# there are too many arguments
if
len
(
args
)
==
1
:
binary
=
args
[
0
]
elif
len
(
args
)
>
1
:
SimpleOpts
.
print_help
()
m5
.
fatal
(
"Expected a binary to execute as positional argument"
)
# create the system we are going to simulate
system
=
System
()
# Set the clock fequency of the system (and all of its children)
system
.
clk_domain
=
SrcClockDomain
()
system
.
clk_domain
.
clock
=
'1GHz'
system
.
clk_domain
.
voltage_domain
=
VoltageDomain
()
# Set up the system
system
.
mem_mode
=
'timing'
# Use timing accesses
system
.
mem_ranges
=
[
AddrRange
(
'512MB'
)]
# Create an address range
# Create a simple CPU
system
.
cpu
=
DerivO3CPU
()
# Create an L1 instruction and data cache
system
.
cpu
.
icache
=
L1ICache
(
opts
)
system
.
cpu
.
dcache
=
L1DCache
(
opts
)
# Connect the instruction and data caches to the CPU
system
.
cpu
.
icache
.
connectCPU
(
system
.
cpu
)
system
.
cpu
.
dcache
.
connectCPU
(
system
.
cpu
)
# Create a memory bus, a coherent crossbar, in this case
system
.
l2bus
=
L2XBar
()
# Hook the CPU ports up to the l2bus
system
.
cpu
.
icache
.
connectBus
(
system
.
l2bus
)
system
.
cpu
.
dcache
.
connectBus
(
system
.
l2bus
)
# Create an L2 cache and connect it to the l2bus
system
.
l2cache
=
L2Cache
(
opts
)
system
.
l2cache
.
connectCPUSideBus
(
system
.
l2bus
)
# Create a memory bus
system
.
membus
=
SystemXBar
()
# Connect the L2 cache to the membus
system
.
l2cache
.
connectMemSideBus
(
system
.
membus
)
# create the interrupt controller for the CPU
system
.
cpu
.
createInterruptController
()
# For x86 only, make sure the interrupts are connected to the memory
# Note: these are directly connected to the memory bus and are not cached
if
m5
.
defines
.
buildEnv
[
'TARGET_ISA'
]
==
"x86"
:
system
.
cpu
.
interrupts
[
0
].
pio
=
system
.
membus
.
master
system
.
cpu
.
interrupts
[
0
].
int_master
=
system
.
membus
.
slave
system
.
cpu
.
interrupts
[
0
].
int_slave
=
system
.
membus
.
master
# Connect the system up to the membus
system
.
system_port
=
system
.
membus
.
slave
# Create a DDR3 memory controller
system
.
mem_ctrl
=
DDR3_1600_x64
()
system
.
mem_ctrl
.
range
=
system
.
mem_ranges
[
0
]
system
.
mem_ctrl
.
port
=
system
.
membus
.
master
# Create a process for a simple "Hello World" application
process
=
LiveProcess
()
# Set the command
# cmd is a list which begins with the executable (like argv)
process
.
cmd
=
[
binary
]
# Set the cpu to use the process as its workload and create thread contexts
system
.
cpu
.
workload
=
process
system
.
cpu
.
createThreads
()