{ "name": null, "sim_quantum": 0, "system": { "kernel": "", "mmap_using_noreserve": false, "kernel_addr_check": true, "membus": { "slave": { "peer": [ "system.cpu.icache_port", "system.cpu.dcache_port", "system.system_port" ], "role": "SLAVE" }, "name": "membus", "snoop_filter": null, "forward_latency": 4, "clk_domain": "system.clk_domain", "system": "system", "width": 16, "eventq_index": 0, "master": { "peer": [ "system.mem_ctrl.port" ], "role": "MASTER" }, "response_latency": 2, "cxx_class": "CoherentXBar", "path": "system.membus", "snoop_response_latency": 4, "type": "CoherentXBar", "use_default_range": false, "frontend_latency": 3 }, "symbolfile": "", "readfile": "", "cxx_class": "System", "load_offset": 0, "work_end_ckpt_count": 0, "memories": [ "system.mem_ctrl" ], "work_begin_ckpt_count": 0, "clk_domain": { "name": "clk_domain", "clock": [ 1000 ], "init_perf_level": 0, "voltage_domain": { "name": "voltage_domain", "eventq_index": 0, "voltage": [ "1.0" ], "cxx_class": "VoltageDomain", "path": "system.clk_domain.voltage_domain", "type": "VoltageDomain" }, "eventq_index": 0, "cxx_class": "SrcClockDomain", "path": "system.clk_domain", "type": "SrcClockDomain", "domain_id": -1 }, "mem_ranges": [ "0:536870911" ], "eventq_index": 0, "work_begin_cpu_id_exit": -1, "dvfs_handler": { "enable": false, "name": "dvfs_handler", "sys_clk_domain": "system.clk_domain", "transition_latency": 100000000, "eventq_index": 0, "cxx_class": "DVFSHandler", "domains": [], "path": "system.dvfs_handler", "type": "DVFSHandler" }, "work_end_exit_count": 0, "type": "System", "cache_line_size": 64, "boot_osflags": "a", "mem_ctrl": { "static_frontend_latency": 10000, "tRFC": 260000, "activation_limit": 4, "in_addr_map": true, "IDD3N2": "0.0", "tWTR": 7500, "IDD52": "0.0", "clk_domain": "system.clk_domain", "channels": 1, "write_buffer_size": 64, "device_bus_width": 8, "VDD": "1.5", "write_high_thresh_perc": 85, "cxx_class": "DRAMCtrl", "bank_groups_per_rank": 0, "IDD2N2": "0.0", "port": { "peer": "system.membus.master[0]", "role": "SLAVE" }, "tCCD_L": 0, "IDD2N": "0.05", "null": false, "IDD2P1": "0.0", "eventq_index": 0, "tRRD": 6000, "tRTW": 2500, "IDD4R": "0.187", "burst_length": 8, "tRTP": 7500, "IDD4W": "0.165", "tWR": 15000, "banks_per_rank": 8, "devices_per_rank": 8, "IDD2P02": "0.0", "IDD6": "0.0", "IDD5": "0.22", "tRCD": 13750, "type": "DRAMCtrl", "IDD3P02": "0.0", "IDD0": "0.075", "IDD62": "0.0", "min_writes_per_switch": 16, "mem_sched_policy": "frfcfs", "IDD02": "0.0", "IDD2P0": "0.0", "ranks_per_channel": 2, "page_policy": "open_adaptive", "IDD4W2": "0.0", "tCS": 2500, "tCL": 13750, "read_buffer_size": 32, "conf_table_reported": true, "tCK": 1250, "tRAS": 35000, "tRP": 13750, "tBURST": 5000, "path": "system.mem_ctrl", "tXP": 0, "tXS": 0, "addr_mapping": "RoRaBaCoCh", "IDD3P0": "0.0", "IDD3P1": "0.0", "IDD3N": "0.057", "name": "mem_ctrl", "tXSDLL": 0, "device_size": 536870912, "dll": true, "tXAW": 30000, "write_low_thresh_perc": 50, "range": "0:536870911", "VDD2": "0.0", "IDD2P12": "0.0", "tRRD_L": 0, "tXPDLL": 0, "IDD4R2": "0.0", "device_rowbuffer_size": 1024, "static_backend_latency": 10000, "max_accesses_per_row": 16, "IDD3P12": "0.0", "tREFI": 7800000 }, "work_cpus_ckpt_count": 0, "work_begin_exit_count": 0, "path": "system", "mem_mode": "timing", "name": "system", "init_param": 0, "system_port": { "peer": "system.membus.slave[2]", "role": "MASTER" }, "load_addr_mask": 1099511627775, "cpu": { "max_insts_any_thread": 0, "do_statistics_insts": true, "numThreads": 1, "fetch1LineSnapWidth": 0, "fetch1ToFetch2BackwardDelay": 1, "fetch1FetchLimit": 1, "executeIssueLimit": 2, "system": "system", "istage2_mmu": { "name": "istage2_mmu", "tlb": "system.cpu.itb", "sys": "system", "stage2_tlb": { "name": "stage2_tlb", "is_stage2": true, "eventq_index": 0, "cxx_class": "ArmISA::TLB", "walker": { "name": "walker", "is_stage2": true, "clk_domain": "system.clk_domain", "sys": "system", "eventq_index": 0, "cxx_class": "ArmISA::TableWalker", "path": "system.cpu.istage2_mmu.stage2_tlb.walker", "type": "ArmTableWalker", "num_squash_per_cycle": 2 }, "path": "system.cpu.istage2_mmu.stage2_tlb", "type": "ArmTLB", "size": 32 }, "eventq_index": 0, "cxx_class": "ArmISA::Stage2MMU", "path": "system.cpu.istage2_mmu", "type": "ArmStage2MMU" }, "executeLSQMaxStoreBufferStoresPerCycle": 2, "function_trace": false, "do_checkpoint_insts": true, "decodeInputWidth": 2, "cxx_class": "MinorCPU", "max_loads_all_threads": 0, "executeMemoryIssueLimit": 1, "decodeCycleInput": true, "max_loads_any_thread": 0, "executeLSQTransfersQueueSize": 2, "clk_domain": "system.clk_domain", "function_trace_start": 0, "cpu_id": -1, "checker": null, "eventq_index": 0, "executeMemoryWidth": 0, "executeBranchDelay": 1, "executeMemoryCommitLimit": 1, "do_quiesce": true, "type": "MinorCPU", "executeCycleInput": true, "executeAllowEarlyMemoryIssue": true, "executeInputBufferSize": 7, "icache_port": { "peer": "system.membus.slave[0]", "role": "MASTER" }, "socket_id": 0, "progress_interval": 0, "isa": [ { "pmu": null, "id_pfr1": 4113, "id_pfr0": 49, "id_isar1": 34677009, "id_isar0": 34607377, "id_isar3": 17899825, "id_isar2": 555950401, "id_isar5": 0, "id_isar4": 268501314, "cxx_class": "ArmISA::ISA", "id_aa64mmfr1_el1": 0, "id_aa64pfr1_el1": 0, "system": "system", "eventq_index": 0, "type": "ArmISA", "id_aa64dfr1_el1": 0, "fpsid": 1090793632, "id_mmfr0": 270536963, "id_mmfr1": 0, "id_mmfr2": 19070976, "id_mmfr3": 34611729, "id_aa64mmfr0_el1": 15728642, "id_aa64dfr0_el1": 1052678, "path": "system.cpu.isa", "id_aa64isar0_el1": 0, "decoderFlavour": "Generic", "name": "isa", "midr": 1091551472, "id_aa64afr0_el1": 0, "id_aa64isar1_el1": 0, "id_aa64afr1_el1": 0, "id_aa64pfr0_el1": 17 } ], "itb": { "name": "itb", "is_stage2": false, "eventq_index": 0, "cxx_class": "ArmISA::TLB", "walker": { "name": "walker", "is_stage2": false, "clk_domain": "system.clk_domain", "sys": "system", "eventq_index": 0, "cxx_class": "ArmISA::TableWalker", "path": "system.cpu.itb.walker", "type": "ArmTableWalker", "num_squash_per_cycle": 2 }, "path": "system.cpu.itb", "type": "ArmTLB", "size": 64 }, "interrupts": [ { "eventq_index": 0, "path": "system.cpu.interrupts", "type": "ArmInterrupts", "name": "interrupts", "cxx_class": "ArmISA::Interrupts" } ], "dcache_port": { "peer": "system.membus.slave[1]", "role": "MASTER" }, "executeFuncUnits": { "name": "executeFuncUnits", "eventq_index": 0, "cxx_class": "MinorFUPool", "path": "system.cpu.executeFuncUnits", "funcUnits": [ { "issueLat": 1, "opLat": 3, "name": "funcUnits0", "cantForwardFromFUIndices": [], "opClasses": { "name": "opClasses", "opClasses": [ { "opClass": "IntAlu", "name": "opClasses", "eventq_index": 0, "cxx_class": "MinorOpClass", "path": "system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses", "type": "MinorOpClass" } ], "eventq_index": 0, "cxx_class": "MinorOpClassSet", "path": "system.cpu.executeFuncUnits.funcUnits0.opClasses", "type": "MinorOpClassSet" }, "eventq_index": 0, "timings": [ { "extraAssumedLat": 0, "description": "Int", "srcRegsRelativeLats": [ 2 ], "suppress": false, "mask": 0, "extraCommitLat": 0, "eventq_index": 0, "opClasses": { "name": "opClasses", "opClasses": [], "eventq_index": 0, "cxx_class": "MinorOpClassSet", "path": "system.cpu.executeFuncUnits.funcUnits0.timings.opClasses", "type": "MinorOpClassSet" }, "cxx_class": "MinorFUTiming", "path": "system.cpu.executeFuncUnits.funcUnits0.timings", "extraCommitLatExpr": null, "type": "MinorFUTiming", "match": 0, "name": "timings" } ], "cxx_class": "MinorFU", "path": "system.cpu.executeFuncUnits.funcUnits0", "type": "MinorFU" }, { "issueLat": 1, "opLat": 3, "name": "funcUnits1", "cantForwardFromFUIndices": [], "opClasses": { "name": "opClasses", "opClasses": [ { "opClass": "IntAlu", "name": "opClasses", "eventq_index": 0, "cxx_class": "MinorOpClass", "path": "system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses", "type": "MinorOpClass" } ], "eventq_index": 0, "cxx_class": "MinorOpClassSet", "path": "system.cpu.executeFuncUnits.funcUnits1.opClasses", "type": "MinorOpClassSet" }, "eventq_index": 0, "timings": [ { "extraAssumedLat": 0, "description": "Int", "srcRegsRelativeLats": [ 2 ], "suppress": false, "mask": 0, "extraCommitLat": 0, "eventq_index": 0, "opClasses": { "name": "opClasses", "opClasses": [], "eventq_index": 0, "cxx_class": "MinorOpClassSet", "path": "system.cpu.executeFuncUnits.funcUnits1.timings.opClasses", "type": "MinorOpClassSet" }, "cxx_class": "MinorFUTiming", "path": "system.cpu.executeFuncUnits.funcUnits1.timings", "extraCommitLatExpr": null, "type": "MinorFUTiming", "match": 0, "name": "timings" } ], "cxx_class": "MinorFU", "path": "system.cpu.executeFuncUnits.funcUnits1", "type": "MinorFU" }, { "issueLat": 1, "opLat": 3, "name": "funcUnits2", "cantForwardFromFUIndices": [], "opClasses": { "name": "opClasses", "opClasses": [ { "opClass": "IntMult", "name": "opClasses", "eventq_index": 0, "cxx_class": "MinorOpClass", "path": "system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses", "type": "MinorOpClass" } ], "eventq_index": 0, "cxx_class": "MinorOpClassSet", "path": "system.cpu.executeFuncUnits.funcUnits2.opClasses", "type": "MinorOpClassSet" }, "eventq_index": 0, "timings": [ { "extraAssumedLat": 0, "description": "Mul", "srcRegsRelativeLats": [ 0 ], "suppress": false, "mask": 0, "extraCommitLat": 0, "eventq_index": 0, "opClasses": { "name": "opClasses", "opClasses": [], "eventq_index": 0, "cxx_class": "MinorOpClassSet", "path": "system.cpu.executeFuncUnits.funcUnits2.timings.opClasses", "type": "MinorOpClassSet" }, "cxx_class": "MinorFUTiming", "path": "system.cpu.executeFuncUnits.funcUnits2.timings", "extraCommitLatExpr": null, "type": "MinorFUTiming", "match": 0, "name": "timings" } ], "cxx_class": "MinorFU", "path": "system.cpu.executeFuncUnits.funcUnits2", "type": "MinorFU" }, { "issueLat": 9, "opLat": 9, "name": "funcUnits3", "cantForwardFromFUIndices": [], "opClasses": { "name": "opClasses", "opClasses": [ { "opClass": "IntDiv", "name": "opClasses", "eventq_index": 0, "cxx_class": "MinorOpClass", "path": "system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses", "type": "MinorOpClass" } ], "eventq_index": 0, "cxx_class": "MinorOpClassSet", "path": "system.cpu.executeFuncUnits.funcUnits3.opClasses", "type": "MinorOpClassSet" }, "eventq_index": 0, "timings": [], "cxx_class": "MinorFU", "path": "system.cpu.executeFuncUnits.funcUnits3", "type": "MinorFU" }, { "issueLat": 1, "opLat": 6, "name": "funcUnits4", "cantForwardFromFUIndices": [], "opClasses": { "name": "opClasses", "opClasses": [ { "opClass": "FloatAdd", "name": "opClasses00", "eventq_index": 0, "cxx_class": "MinorOpClass", "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00", "type": "MinorOpClass" }, { "opClass": "FloatCmp", "name": "opClasses01", "eventq_index": 0, "cxx_class": "MinorOpClass", "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01", "type": "MinorOpClass" }, { "opClass": "FloatCvt", "name": "opClasses02", "eventq_index": 0, "cxx_class": "MinorOpClass", "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02", "type": "MinorOpClass" }, { "opClass": "FloatMult", "name": "opClasses03", "eventq_index": 0, "cxx_class": "MinorOpClass", "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03", "type": "MinorOpClass" }, { "opClass": "FloatDiv", "name": "opClasses04", "eventq_index": 0, "cxx_class": "MinorOpClass", "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04", "type": "MinorOpClass" }, { "opClass": "FloatSqrt", "name": "opClasses05", "eventq_index": 0, "cxx_class": "MinorOpClass", "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05", "type": "MinorOpClass" }, { "opClass": "SimdAdd", "name": "opClasses06", "eventq_index": 0, "cxx_class": "MinorOpClass", "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06", "type": "MinorOpClass" }, { "opClass": "SimdAddAcc", "name": "opClasses07", "eventq_index": 0, "cxx_class": "MinorOpClass", "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07", "type": "MinorOpClass" }, { "opClass": "SimdAlu", "name": "opClasses08", "eventq_index": 0, "cxx_class": "MinorOpClass", "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08", "type": "MinorOpClass" }, { "opClass": "SimdCmp", "name": "opClasses09", "eventq_index": 0, "cxx_class": "MinorOpClass", "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09", "type": "MinorOpClass" }, { "opClass": "SimdCvt", "name": "opClasses10", "eventq_index": 0, "cxx_class": "MinorOpClass", "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10", "type": "MinorOpClass" }, { "opClass": "SimdMisc", "name": "opClasses11", "eventq_index": 0, "cxx_class": "MinorOpClass", "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11", "type": "MinorOpClass" }, { "opClass": "SimdMult", "name": "opClasses12", "eventq_index": 0, "cxx_class": "MinorOpClass", "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12", "type": "MinorOpClass" }, { "opClass": "SimdMultAcc", "name": "opClasses13", "eventq_index": 0, "cxx_class": "MinorOpClass", "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13", "type": "MinorOpClass" }, { "opClass": "SimdShift", "name": "opClasses14", "eventq_index": 0, "cxx_class": "MinorOpClass", "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14", "type": "MinorOpClass" }, { "opClass": "SimdShiftAcc", "name": "opClasses15", "eventq_index": 0, "cxx_class": "MinorOpClass", "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15", "type": "MinorOpClass" }, { "opClass": "SimdSqrt", "name": "opClasses16", "eventq_index": 0, "cxx_class": "MinorOpClass", "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16", "type": "MinorOpClass" }, { "opClass": "SimdFloatAdd", "name": "opClasses17", "eventq_index": 0, "cxx_class": "MinorOpClass", "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17", "type": "MinorOpClass" }, { "opClass": "SimdFloatAlu", "name": "opClasses18", "eventq_index": 0, "cxx_class": "MinorOpClass", "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18", "type": "MinorOpClass" }, { "opClass": "SimdFloatCmp", "name": "opClasses19", "eventq_index": 0, "cxx_class": "MinorOpClass", "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19", "type": "MinorOpClass" }, { "opClass": "SimdFloatCvt", "name": "opClasses20", "eventq_index": 0, "cxx_class": "MinorOpClass", "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20", "type": "MinorOpClass" }, { "opClass": "SimdFloatDiv", "name": "opClasses21", "eventq_index": 0, "cxx_class": "MinorOpClass", "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21", "type": "MinorOpClass" }, { "opClass": "SimdFloatMisc", "name": "opClasses22", "eventq_index": 0, "cxx_class": "MinorOpClass", "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22", "type": "MinorOpClass" }, { "opClass": "SimdFloatMult", "name": "opClasses23", "eventq_index": 0, "cxx_class": "MinorOpClass", "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23", "type": "MinorOpClass" }, { "opClass": "SimdFloatMultAcc", "name": "opClasses24", "eventq_index": 0, "cxx_class": "MinorOpClass", "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24", "type": "MinorOpClass" }, { "opClass": "SimdFloatSqrt", "name": "opClasses25", "eventq_index": 0, "cxx_class": "MinorOpClass", "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25", "type": "MinorOpClass" } ], "eventq_index": 0, "cxx_class": "MinorOpClassSet", "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses", "type": "MinorOpClassSet" }, "eventq_index": 0, "timings": [ { "extraAssumedLat": 0, "description": "FloatSimd", "srcRegsRelativeLats": [ 2 ], "suppress": false, "mask": 0, "extraCommitLat": 0, "eventq_index": 0, "opClasses": { "name": "opClasses", "opClasses": [], "eventq_index": 0, "cxx_class": "MinorOpClassSet", "path": "system.cpu.executeFuncUnits.funcUnits4.timings.opClasses", "type": "MinorOpClassSet" }, "cxx_class": "MinorFUTiming", "path": "system.cpu.executeFuncUnits.funcUnits4.timings", "extraCommitLatExpr": null, "type": "MinorFUTiming", "match": 0, "name": "timings" } ], "cxx_class": "MinorFU", "path": "system.cpu.executeFuncUnits.funcUnits4", "type": "MinorFU" }, { "issueLat": 1, "opLat": 1, "name": "funcUnits5", "cantForwardFromFUIndices": [], "opClasses": { "name": "opClasses", "opClasses": [ { "opClass": "MemRead", "name": "opClasses0", "eventq_index": 0, "cxx_class": "MinorOpClass", "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0", "type": "MinorOpClass" }, { "opClass": "MemWrite", "name": "opClasses1", "eventq_index": 0, "cxx_class": "MinorOpClass", "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1", "type": "MinorOpClass" } ], "eventq_index": 0, "cxx_class": "MinorOpClassSet", "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses", "type": "MinorOpClassSet" }, "eventq_index": 0, "timings": [ { "extraAssumedLat": 2, "description": "Mem", "srcRegsRelativeLats": [ 1 ], "suppress": false, "mask": 0, "extraCommitLat": 0, "eventq_index": 0, "opClasses": { "name": "opClasses", "opClasses": [], "eventq_index": 0, "cxx_class": "MinorOpClassSet", "path": "system.cpu.executeFuncUnits.funcUnits5.timings.opClasses", "type": "MinorOpClassSet" }, "cxx_class": "MinorFUTiming", "path": "system.cpu.executeFuncUnits.funcUnits5.timings", "extraCommitLatExpr": null, "type": "MinorFUTiming", "match": 0, "name": "timings" } ], "cxx_class": "MinorFU", "path": "system.cpu.executeFuncUnits.funcUnits5", "type": "MinorFU" }, { "issueLat": 1, "opLat": 1, "name": "funcUnits6", "cantForwardFromFUIndices": [], "opClasses": { "name": "opClasses", "opClasses": [ { "opClass": "IprAccess", "name": "opClasses0", "eventq_index": 0, "cxx_class": "MinorOpClass", "path": "system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0", "type": "MinorOpClass" }, { "opClass": "InstPrefetch", "name": "opClasses1", "eventq_index": 0, "cxx_class": "MinorOpClass", "path": "system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1", "type": "MinorOpClass" } ], "eventq_index": 0, "cxx_class": "MinorOpClassSet", "path": "system.cpu.executeFuncUnits.funcUnits6.opClasses", "type": "MinorOpClassSet" }, "eventq_index": 0, "timings": [], "cxx_class": "MinorFU", "path": "system.cpu.executeFuncUnits.funcUnits6", "type": "MinorFU" } ], "type": "MinorFUPool" }, "switched_out": false, "max_insts_all_threads": 0, "dstage2_mmu": { "name": "dstage2_mmu", "tlb": "system.cpu.dtb", "sys": "system", "stage2_tlb": { "name": "stage2_tlb", "is_stage2": true, "eventq_index": 0, "cxx_class": "ArmISA::TLB", "walker": { "name": "walker", "is_stage2": true, "clk_domain": "system.clk_domain", "sys": "system", "eventq_index": 0, "cxx_class": "ArmISA::TableWalker", "path": "system.cpu.dstage2_mmu.stage2_tlb.walker", "type": "ArmTableWalker", "num_squash_per_cycle": 2 }, "path": "system.cpu.dstage2_mmu.stage2_tlb", "type": "ArmTLB", "size": 32 }, "eventq_index": 0, "cxx_class": "ArmISA::Stage2MMU", "path": "system.cpu.dstage2_mmu", "type": "ArmStage2MMU" }, "fetch2InputBufferSize": 2, "profile": 0, "fetch2ToDecodeForwardDelay": 1, "executeInputWidth": 2, "decodeToExecuteForwardDelay": 1, "executeLSQRequestsQueueSize": 1, "fetch2CycleInput": true, "executeMaxAccessesInMemory": 2, "enableIdling": true, "executeLSQStoreBufferSize": 5, "workload": [ { "uid": 100, "pid": 100, "kvmInSE": false, "cxx_class": "LiveProcess", "executable": "", "drivers": [], "system": "system", "gid": 100, "eventq_index": 0, "env": [], "input": "cin", "ppid": 99, "type": "LiveProcess", "cwd": "", "simpoint": 0, "euid": 100, "path": "system.cpu.workload", "max_stack_size": 67108864, "name": "workload", "cmd": [ "/home/vagrant/advanced_computer_architecture/exercises/blatt01/exec/automotive/basicmath/basicmath_small" ], "errout": "cerr", "useArchPT": false, "egid": 100, "output": "cout" } ], "name": "cpu", "executeSetTraceTimeOnIssue": false, "dtb": { "name": "dtb", "is_stage2": false, "eventq_index": 0, "cxx_class": "ArmISA::TLB", "walker": { "name": "walker", "is_stage2": false, "clk_domain": "system.clk_domain", "sys": "system", "eventq_index": 0, "cxx_class": "ArmISA::TableWalker", "path": "system.cpu.dtb.walker", "type": "ArmTableWalker", "num_squash_per_cycle": 2 }, "path": "system.cpu.dtb", "type": "ArmTLB", "size": 64 }, "simpoint_start_insts": [], "executeSetTraceTimeOnCommit": true, "tracer": { "eventq_index": 0, "path": "system.cpu.tracer", "type": "ExeTracer", "name": "tracer", "cxx_class": "Trace::ExeTracer" }, "executeCommitLimit": 2, "fetch1LineWidth": 0, "branchPred": { "choiceCtrBits": 2, "name": "branchPred", "globalCtrBits": 2, "numThreads": 1, "localHistoryTableSize": 2048, "choicePredictorSize": 8192, "instShiftAmt": 2, "localCtrBits": 2, "eventq_index": 0, "BTBTagSize": 16, "BTBEntries": 4096, "cxx_class": "TournamentBP", "path": "system.cpu.branchPred", "localPredictorSize": 2048, "type": "TournamentBP", "RASSize": 16, "globalPredictorSize": 8192 }, "path": "system.cpu", "fetch1ToFetch2ForwardDelay": 1, "decodeInputBufferSize": 3 }, "multi_thread": false, "exit_on_work_items": false, "work_item_id": -1, "num_work_ids": 16 }, "time_sync_period": 100000000000, "eventq_index": 0, "time_sync_spin_threshold": 100000000, "cxx_class": "Root", "path": "root", "time_sync_enable": false, "type": "Root", "full_system": false }