An introduction to gem5

Introduction to gem5

  • Welcome to the redesigned exercises.

    • Give feedback wether you like this
  • Goals

    • Strengthen understanding of the Lectures
    • Provide some tools for state of the art CA research
  • Focus on gem5

    • most widely used Simulator in CA-Research
    • Lot's of Publications
  • Exercise sessions are for you

    • Please participate and ask questions

gem5 Developers

Developed by a wide Range of Industrial and Academic Institutions


gem5 Basics

  1. gem5's components can be rearranged, parameterized, extended or replaced easily to suit your needs.
  2. It simulates the passing of time as a series of discrete events.
  3. Its intended use is to simulate one or more computer systems in various ways.
  4. It's more than just a simulator; it's a simulator platform that lets you use as many of its premade components as you want to build up your own simulation system.

Other SImulators

Simulator Accuracy Supported processor architectures License Development Activity
Simics Functionally accurate Alpha, ARM, MIPS, PowerPC, SPARC and x86 Private Yes
qemu Functionally accurate x86, PowerPC, ARM, Sparc, MicroBlaze, Mico32 and others Open Yes
PTLsim Cycle accurate x86 Open Yes
SimpleScalar Cycle accurate Alpha, ARM, PowerPC and x86 Open No
OVPsim Instruction accurate Open RISC, ARM, ARC, MIPS, PowerPC, MicroBlaze and others Private Yes
GEM5 Cycle accurate Alpha, ARM, x86, SPARC, PowerPC and MIPS Open Yes

gem5 Features

  • Configurable CPU models

    • Simple one-IPC (SimpleAtomic/Timing)
    • Detailed in-order execution (InOrder)
    • Detailed out-of-order execution (O3)
  • Pluggable memory system

    • Stitch memory system together out of components
  • Device Models

    • Enough device models to boot Linux
  • Many ISAs

gem5 abstraction levels

gem5 abstraction

Building gem5

Building gem5

  • Recommended virtual machine images with gem5 preinstalled

  • Should build on 64 Bit Linux, MacOSX, FreeBSD

  • For details Exercise Sheet 01

Building gem5

  • build/<isa>/<binary>

  • ISAs:


We use ARM

  • Binaries
    • gem5.debug debug build, symbols, tracing, assert
    • gem5.opt optimized build, symbols, tracing, assert
    • optimized build, no debugging, no symbols, no tracing, no assertions
    • + profiling support

We use gem5.opt

gem5 simulation modes

gem5 simulation modes

  • Full system (FS)

    • For booting operating systems
    • Models bare hardware, including devices
    • Interrupts, exceptions, privileged instructions, fault handlers
    • Simulated UART output
    • Simulated frame buffer output
    • complex to configure
  • Syscall emulation (SE)

    • For running individual applications, or set of applications on MP
    • Models user-visible ISA plus common system calls
    • System calls emulated, typically by calling host OS
    • Simplified address translation model, no scheduling
    • syscall emulation mode

Sample Syscall emulation Mode

Sample Full system ode

Full systme mode

Syscall Emulation

gem5 simulation architecture

gem5 architecture


  • Everything you care about is an object (C++/Python)

    • Assembled using Python, simulated using C++
    • Derived from SimObject base class
    • Common code for creation, configuration parameters, naming, checkpointing, etc.
  • Uniform method-based APIs for object types

    • CPUs, caches, memory, etc.
  • Easy reuse of system components

    • Functional vs. detailed CPU
    • Conventional vs. indirect-index cache
  • Easy replication: cores, multiple systems

  • MemObjects are special kinds of SimObjects that can be connect using ports

Ports / MemObjects

  • Used for connecting MemObjects together

    • e.g. enable a CPU to issue reads/writes to a memory
  • Correspond to real structural ports on system components

    • e.g. CPU has an instruction and a data port
  • Ports have distinct roles, and always appear in pairs

  • A MasterPort is connected to a SlavePort

    • Send and receive function pairs transport packets
  • Quite Similar to TLM-2 initiator and target socket ()

gem5 ports

Full System Simulation

Full System Simulation

Full System SImulation

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