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Commit e94bda4b authored by Christoph Gerum's avatar Christoph Gerum
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Exercise Sheet 03

parent c0e4c8a8
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aufgaben/blatt01/hello.c 0 → 100644
View file @ e94bda4b
#include <stdio.h>
int main(int argc, char **argv){
printf("Hello World!\n");
}
aufgaben/blatt01/m5out/config.ini 0 → 100644
View file @ e94bda4b
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu dvfs_handler mem_ctrl membus
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
eventq_index=0
init_param=0
kernel=
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=0:536870911
memories=system.mem_ctrl
mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[2]
[system.clk_domain]
type=SrcClockDomain
children=voltage_domain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.clk_domain.voltage_domain
[system.clk_domain.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000
[system.cpu]
type=TimingSimpleCPU
children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload
branchPred=Null
checker=Null
clk_domain=system.clk_domain
cpu_id=-1
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu.dstage2_mmu
dtb=system.cpu.dtb
eventq_index=0
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
istage2_mmu=system.cpu.istage2_mmu
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.membus.slave[1]
icache_port=system.membus.slave[0]
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
sys=system
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
[system.cpu.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
[system.cpu.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
clk_domain=system.clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
[system.cpu.interrupts]
type=ArmInterrupts
eventq_index=0
[system.cpu.isa]
type=ArmISA
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
id_pfr0=49
id_pfr1=4113
midr=1091551472
pmu=Null
system=system
[system.cpu.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
sys=system
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.istage2_mmu.stage2_tlb.walker
[system.cpu.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
[system.cpu.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
clk_domain=system.clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
sys=system
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
cmd=./hello.elf
cwd=
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
useArchPT=false
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.mem_ctrl]
type=DRAMCtrl
IDD0=0.064000
IDD02=0.004000
IDD2N=0.050000
IDD2N2=0.000000
IDD2P0=0.000000
IDD2P02=0.000000
IDD2P1=0.000000
IDD2P12=0.000000
IDD3N=0.067000
IDD3N2=0.003000
IDD3P0=0.000000
IDD3P02=0.000000
IDD3P1=0.000000
IDD3P12=0.000000
IDD4R=0.160000
IDD4R2=0.000000
IDD4W=0.180000
IDD4W2=0.000000
IDD5=0.192000
IDD52=0.000000
IDD6=0.000000
IDD62=0.000000
VDD=1.200000
VDD2=2.500000
activation_limit=4
addr_mapping=RoRaBaCoCh
bank_groups_per_rank=4
banks_per_rank=16
burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
page_policy=open_adaptive
range=0:536870911
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=3333
tCCD_L=5000
tCK=833
tCL=14160
tCS=1666
tRAS=32000
tRCD=14160
tREFI=7800000
tRFC=350000
tRP=14160
tRRD=3300
tRRD_L=4900
tRTP=7500
tRTW=1666
tWR=15000
tWTR=5000
tXAW=21000
tXP=0
tXPDLL=0
tXS=0
tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
port=system.membus.master[0]
[system.membus]
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
response_latency=2
snoop_filter=Null
snoop_response_latency=4
system=system
use_default_range=false
width=16
master=system.mem_ctrl.port
slave=system.cpu.icache_port system.cpu.dcache_port system.system_port
aufgaben/blatt01/m5out/config.json 0 → 100644
View file @ e94bda4b
{
"name": null,
"sim_quantum": 0,
"system": {
"kernel": "",
"mmap_using_noreserve": false,
"kernel_addr_check": true,
"membus": {
"slave": {
"peer": [
"system.cpu.icache_port",
"system.cpu.dcache_port",
"system.system_port"
],
"role": "SLAVE"
},
"name": "membus",
"snoop_filter": null,
"forward_latency": 4,
"clk_domain": "system.clk_domain",
"system": "system",
"width": 16,
"eventq_index": 0,
"master": {
"peer": [
"system.mem_ctrl.port"
],
"role": "MASTER"
},
"response_latency": 2,
"cxx_class": "CoherentXBar",
"path": "system.membus",
"snoop_response_latency": 4,
"type": "CoherentXBar",
"use_default_range": false,
"frontend_latency": 3
},
"symbolfile": "",
"readfile": "",
"cxx_class": "System",
"load_offset": 0,
"work_end_ckpt_count": 0,
"memories": [
"system.mem_ctrl"
],
"work_begin_ckpt_count": 0,
"clk_domain": {
"name": "clk_domain",
"clock": [
500
],
"init_perf_level": 0,
"voltage_domain": {
"name": "voltage_domain",
"eventq_index": 0,
"voltage": [
"1.0"
],
"cxx_class": "VoltageDomain",
"path": "system.clk_domain.voltage_domain",
"type": "VoltageDomain"
},
"eventq_index": 0,
"cxx_class": "SrcClockDomain",
"path": "system.clk_domain",
"type": "SrcClockDomain",
"domain_id": -1
},
"mem_ranges": [
"0:536870911"
],
"eventq_index": 0,
"dvfs_handler": {
"enable": false,
"name": "dvfs_handler",
"sys_clk_domain": "system.clk_domain",
"transition_latency": 100000000,
"eventq_index": 0,
"cxx_class": "DVFSHandler",
"domains": [],
"path": "system.dvfs_handler",
"type": "DVFSHandler"
},
"work_end_exit_count": 0,
"type": "System",
"cache_line_size": 64,
"boot_osflags": "a",
"mem_ctrl": {
"static_frontend_latency": 10000,
"tRFC": 350000,
"activation_limit": 4,
"in_addr_map": true,
"IDD3N2": "0.003",
"tWTR": 5000,
"IDD52": "0.0",
"clk_domain": "system.clk_domain",
"channels": 1,
"write_buffer_size": 64,
"device_bus_width": 8,
"VDD": "1.2",
"write_high_thresh_perc": 85,
"cxx_class": "DRAMCtrl",
"bank_groups_per_rank": 4,
"IDD2N2": "0.0",
"port": {
"peer": "system.membus.master[0]",
"role": "SLAVE"
},
"tCCD_L": 5000,
"IDD2N": "0.05",
"null": false,
"IDD2P1": "0.0",
"eventq_index": 0,
"tRRD": 3300,
"tRTW": 1666,
"IDD4R": "0.16",
"burst_length": 8,
"tRTP": 7500,
"IDD4W": "0.18",
"tWR": 15000,
"banks_per_rank": 16,
"devices_per_rank": 8,
"IDD2P02": "0.0",
"IDD6": "0.0",
"IDD5": "0.192",
"tRCD": 14160,
"type": "DRAMCtrl",
"IDD3P02": "0.0",
"IDD0": "0.064",
"IDD62": "0.0",
"min_writes_per_switch": 16,
"mem_sched_policy": "frfcfs",
"IDD02": "0.004",
"IDD2P0": "0.0",
"ranks_per_channel": 2,
"page_policy": "open_adaptive",
"IDD4W2": "0.0",
"tCS": 1666,
"tCL": 14160,
"read_buffer_size": 32,
"conf_table_reported": true,
"tCK": 833,
"tRAS": 32000,
"tRP": 14160,
"tBURST": 3333,
"path": "system.mem_ctrl",
"tXP": 0,
"tXS": 0,
"addr_mapping": "RoRaBaCoCh",
"IDD3P0": "0.0",
"IDD3P1": "0.0",
"IDD3N": "0.067",
"name": "mem_ctrl",
"tXSDLL": 0,
"device_size": 536870912,
"dll": true,
"tXAW": 21000,
"write_low_thresh_perc": 50,
"range": "0:536870911",
"VDD2": "2.5",
"IDD2P12": "0.0",
"tRRD_L": 4900,
"tXPDLL": 0,
"IDD4R2": "0.0",
"device_rowbuffer_size": 1024,
"static_backend_latency": 10000,
"max_accesses_per_row": 16,
"IDD3P12": "0.0",
"tREFI": 7800000
},
"work_cpus_ckpt_count": 0,
"work_begin_exit_count": 0,
"path": "system",
"mem_mode": "timing",
"name": "system",
"init_param": 0,
"system_port": {
"peer": "system.membus.slave[2]",
"role": "MASTER"
},
"load_addr_mask": 1099511627775,
"cpu": {
"do_statistics_insts": true,
"numThreads": 1,
"itb": {
"name": "itb",
"is_stage2": false,
"eventq_index": 0,
"cxx_class": "ArmISA::TLB",
"walker": {
"name": "walker",
"is_stage2": false,
"clk_domain": "system.clk_domain",
"sys": "system",
"eventq_index": 0,
"cxx_class": "ArmISA::TableWalker",
"path": "system.cpu.itb.walker",
"type": "ArmTableWalker",
"num_squash_per_cycle": 2
},
"path": "system.cpu.itb",
"type": "ArmTLB",
"size": 64
},
"system": "system",
"istage2_mmu": {
"name": "istage2_mmu",
"tlb": "system.cpu.itb",
"sys": "system",
"stage2_tlb": {
"name": "stage2_tlb",
"is_stage2": true,
"eventq_index": 0,
"cxx_class": "ArmISA::TLB",
"walker": {
"name": "walker",
"is_stage2": true,
"clk_domain": "system.clk_domain",
"sys": "system",
"eventq_index": 0,
"cxx_class": "ArmISA::TableWalker",
"path": "system.cpu.istage2_mmu.stage2_tlb.walker",
"type": "ArmTableWalker",
"num_squash_per_cycle": 2
},
"path": "system.cpu.istage2_mmu.stage2_tlb",
"type": "ArmTLB",
"size": 32
},
"eventq_index": 0,
"cxx_class": "ArmISA::Stage2MMU",
"path": "system.cpu.istage2_mmu",
"type": "ArmStage2MMU"
},
"function_trace": false,
"do_checkpoint_insts": true,
"cxx_class": "TimingSimpleCPU",
"max_loads_all_threads": 0,
"clk_domain": "system.clk_domain",
"function_trace_start": 0,
"cpu_id": -1,
"checker": null,
"eventq_index": 0,
"do_quiesce": true,
"type": "TimingSimpleCPU",