From 23d5f70d9659a3251c1df45dd63563266e77604a Mon Sep 17 00:00:00 2001 From: Christoph Gerum Date: Thu, 14 Apr 2016 19:43:40 +0200 Subject: [PATCH] Finish config --- aufgaben/blatt01/blatt01.md | 30 +- .../m5out-automotive-MinorCPU/config.ini | 761 ---------- .../m5out-automotive-MinorCPU/config.json | 1010 -------------- .../m5out-automotive-MinorCPU/stats.txt | 442 ------ .../config.ini | 331 ----- .../config.json | 411 ------ .../stats.txt | 481 ------- aufgaben/blatt01/m5out/config.ini | 930 ------------- aufgaben/blatt01/m5out/config.json | 1222 ----------------- aufgaben/blatt01/m5out/stats.txt | 0 aufgaben/blatt01/simple.py | 21 +- 11 files changed, 44 insertions(+), 5595 deletions(-) delete mode 100644 aufgaben/blatt01/m5out-automotive-MinorCPU/config.ini delete mode 100644 aufgaben/blatt01/m5out-automotive-MinorCPU/config.json delete mode 100644 aufgaben/blatt01/m5out-automotive-MinorCPU/stats.txt delete mode 100644 aufgaben/blatt01/m5out-automotive-TimingSimpleCPU/config.ini delete mode 100644 aufgaben/blatt01/m5out-automotive-TimingSimpleCPU/config.json delete mode 100644 aufgaben/blatt01/m5out-automotive-TimingSimpleCPU/stats.txt delete mode 100644 aufgaben/blatt01/m5out/config.ini delete mode 100644 aufgaben/blatt01/m5out/config.json delete mode 100644 aufgaben/blatt01/m5out/stats.txt diff --git a/aufgaben/blatt01/blatt01.md b/aufgaben/blatt01/blatt01.md index 7e287c8..ce02371 100644 --- a/aufgaben/blatt01/blatt01.md +++ b/aufgaben/blatt01/blatt01.md @@ -54,9 +54,9 @@ Für diese Aufgabe ist **keine** Abgabe notwendig. ## Aufgabe 2: Einführung in Instruktionssatzsimulation -Schreiben sie ein Programm das ```Hello World!``` ausgibt in C und kompilieren Sie dieses für ARM. +Schreiben sie ein Programm das ```Hello World!``` ausgibt in C und kompilieren Sie dieses wie folgt für ARM. - + arm-linux-gnueabihf-gcc -static -O3 hello.c -o hello.elf Führen Sie dieses im gem5-Simulator aus. Verwenden Sie dafür die bereitgestellte Config-Datei se.py @@ -119,11 +119,11 @@ system.mem_ranges = [AddrRange('512MB')] ``` python system.cpu = TimingSimpleCPU() +system.cpu.createInterruptController() ``` - ``` python -system.membus = CoherentBus() +system.membus = SystemXBar() ``` ``` python @@ -132,10 +132,30 @@ system.cpu.dcache_port = system.membus.slave ``` ``` python -system.mem_ctrl = DDR3_1600_x64() +system.mem_ctrl = DDR4_2400_x64() system.mem_ctrl.range = system.mem_ranges[0] system.mem_ctrl.port = system.membus.master ``` +``` python +process = LiveProcess() +process.cmd = ['./hello.elf'] +system.cpu.workload = process +system.cpu.createThreads() +``` + +``` python +root = Root(full_system = False, system = system) + +m5.instantiate() +``` + +``` python +print "Beginning simulation!" + +exit_event = m5.simulate() + +print 'Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause()) +``` Die Konfigurationsdatei finden Sie auch unter [aufgaben/blatt01/simple.py](/aufgaben/blatt01/simple.py). diff --git a/aufgaben/blatt01/m5out-automotive-MinorCPU/config.ini b/aufgaben/blatt01/m5out-automotive-MinorCPU/config.ini deleted file mode 100644 index ecab627..0000000 --- a/aufgaben/blatt01/m5out-automotive-MinorCPU/config.ini +++ /dev/null @@ -1,761 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu dvfs_handler mem_ctrl membus -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges=0:536870911 -memories=system.mem_ctrl -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -readfile= -symbolfile= -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[2] - -[system.clk_domain] -type=SrcClockDomain -children=voltage_domain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.clk_domain.voltage_domain - -[system.clk_domain.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - -[system.cpu] -type=MinorCPU -children=branchPred dstage2_mmu dtb executeFuncUnits interrupts isa istage2_mmu itb tracer workload -branchPred=system.cpu.branchPred -checker=Null -clk_domain=system.clk_domain -cpu_id=-1 -decodeCycleInput=true -decodeInputBufferSize=3 -decodeInputWidth=2 -decodeToExecuteForwardDelay=1 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu.dstage2_mmu -dtb=system.cpu.dtb -enableIdling=true -eventq_index=0 -executeAllowEarlyMemoryIssue=true -executeBranchDelay=1 -executeCommitLimit=2 -executeCycleInput=true -executeFuncUnits=system.cpu.executeFuncUnits -executeInputBufferSize=7 -executeInputWidth=2 -executeIssueLimit=2 -executeLSQMaxStoreBufferStoresPerCycle=2 -executeLSQRequestsQueueSize=1 -executeLSQStoreBufferSize=5 -executeLSQTransfersQueueSize=2 -executeMaxAccessesInMemory=2 -executeMemoryCommitLimit=1 -executeMemoryIssueLimit=1 -executeMemoryWidth=0 -executeSetTraceTimeOnCommit=true -executeSetTraceTimeOnIssue=false -fetch1FetchLimit=1 -fetch1LineSnapWidth=0 -fetch1LineWidth=0 -fetch1ToFetch2BackwardDelay=1 -fetch1ToFetch2ForwardDelay=1 -fetch2CycleInput=true -fetch2InputBufferSize=2 -fetch2ToDecodeForwardDelay=1 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -istage2_mmu=system.cpu.istage2_mmu -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.membus.slave[1] -icache_port=system.membus.slave[0] - -[system.cpu.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 - -[system.cpu.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.dtb - -[system.cpu.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.dstage2_mmu.stage2_tlb.walker - -[system.cpu.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -sys=system - -[system.cpu.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.dtb.walker - -[system.cpu.dtb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -sys=system - -[system.cpu.executeFuncUnits] -type=MinorFUPool -children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 -eventq_index=0 -funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 - -[system.cpu.executeFuncUnits.funcUnits0] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits0.timings - -[system.cpu.executeFuncUnits.funcUnits0.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits0.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits1] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits1.timings - -[system.cpu.executeFuncUnits.funcUnits1.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits1.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits2] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits2.timings - -[system.cpu.executeFuncUnits.funcUnits2.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntMult - -[system.cpu.executeFuncUnits.funcUnits2.timings] -type=MinorFUTiming -children=opClasses -description=Mul -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses -srcRegsRelativeLats=0 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits3] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=9 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses -opLat=9 -timings= - -[system.cpu.executeFuncUnits.funcUnits3.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntDiv - -[system.cpu.executeFuncUnits.funcUnits4] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses -opLat=6 -timings=system.cpu.executeFuncUnits.funcUnits4.timings - -[system.cpu.executeFuncUnits.funcUnits4.opClasses] -type=MinorOpClassSet -children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] -type=MinorOpClass -eventq_index=0 -opClass=FloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] -type=MinorOpClass -eventq_index=0 -opClass=FloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] -type=MinorOpClass -eventq_index=0 -opClass=FloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] -type=MinorOpClass -eventq_index=0 -opClass=FloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] -type=MinorOpClass -eventq_index=0 -opClass=FloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] -type=MinorOpClass -eventq_index=0 -opClass=FloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] -type=MinorOpClass -eventq_index=0 -opClass=SimdAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] -type=MinorOpClass -eventq_index=0 -opClass=SimdAddAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] -type=MinorOpClass -eventq_index=0 -opClass=SimdAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] -type=MinorOpClass -eventq_index=0 -opClass=SimdCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] -type=MinorOpClass -eventq_index=0 -opClass=SimdCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] -type=MinorOpClass -eventq_index=0 -opClass=SimdMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] -type=MinorOpClass -eventq_index=0 -opClass=SimdMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] -type=MinorOpClass -eventq_index=0 -opClass=SimdMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] -type=MinorOpClass -eventq_index=0 -opClass=SimdShift - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] -type=MinorOpClass -eventq_index=0 -opClass=SimdShiftAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] -type=MinorOpClass -eventq_index=0 -opClass=SimdSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.timings] -type=MinorFUTiming -children=opClasses -description=FloatSimd -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 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-[system.cpu.executeFuncUnits.funcUnits5.timings] -type=MinorFUTiming -children=opClasses -description=Mem -eventq_index=0 -extraAssumedLat=2 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses -srcRegsRelativeLats=1 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits6] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses -opLat=1 -timings= - -[system.cpu.executeFuncUnits.funcUnits6.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=IprAccess - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=InstPrefetch - -[system.cpu.interrupts] -type=ArmInterrupts -eventq_index=0 - -[system.cpu.isa] -type=ArmISA -decoderFlavour=Generic -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 -id_aa64pfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 -midr=1091551472 -pmu=Null -system=system - -[system.cpu.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.istage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.itb - -[system.cpu.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.istage2_mmu.stage2_tlb.walker - -[system.cpu.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -sys=system - -[system.cpu.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.itb.walker - -[system.cpu.itb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -sys=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=/home/vagrant/advanced_computer_architecture/exercises/blatt01/exec/automotive/basicmath/basicmath_small -cwd= -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable= -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.mem_ctrl] -type=DRAMCtrl -IDD0=0.075000 -IDD02=0.000000 -IDD2N=0.050000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.000000 -IDD2P12=0.000000 -IDD3N=0.057000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.000000 -IDD3P12=0.000000 -IDD4R=0.187000 -IDD4R2=0.000000 -IDD4W=0.165000 -IDD4W2=0.000000 -IDD5=0.220000 -IDD52=0.000000 -IDD6=0.000000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -page_policy=open_adaptive -range=0:536870911 -ranks_per_channel=2 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/dev/null @@ -1,1010 +0,0 @@ -{ - "name": null, - "sim_quantum": 0, - "system": { - "kernel": "", - "mmap_using_noreserve": false, - "kernel_addr_check": true, - "membus": { - "slave": { - "peer": [ - "system.cpu.icache_port", - "system.cpu.dcache_port", - "system.system_port" - ], - "role": "SLAVE" - }, - "name": "membus", - "snoop_filter": null, - "forward_latency": 4, - "clk_domain": "system.clk_domain", - "system": "system", - "width": 16, - "eventq_index": 0, - "master": { - "peer": [ - "system.mem_ctrl.port" - ], - "role": "MASTER" - }, - "response_latency": 2, - "cxx_class": "CoherentXBar", - "path": "system.membus", - "snoop_response_latency": 4, - "type": "CoherentXBar", - "use_default_range": false, - "frontend_latency": 3 - }, - "symbolfile": "", - "readfile": "", - "cxx_class": "System", - "load_offset": 0, - "work_end_ckpt_count": 0, - "memories": [ - "system.mem_ctrl" - ], - "work_begin_ckpt_count": 0, - "clk_domain": { - "name": "clk_domain", - "clock": [ - 1000 - ], - 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"system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24", - "type": "MinorOpClass" - }, - { - "opClass": "SimdFloatSqrt", - "name": "opClasses25", - "eventq_index": 0, - "cxx_class": "MinorOpClass", - "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25", - "type": "MinorOpClass" - } - ], - "eventq_index": 0, - "cxx_class": "MinorOpClassSet", - "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses", - "type": "MinorOpClassSet" - }, - "eventq_index": 0, - "timings": [ - { - "extraAssumedLat": 0, - "description": "FloatSimd", - "srcRegsRelativeLats": [ - 2 - ], - "suppress": false, - "mask": 0, - "extraCommitLat": 0, - "eventq_index": 0, - "opClasses": { - "name": "opClasses", - "opClasses": [], - "eventq_index": 0, - "cxx_class": "MinorOpClassSet", - "path": "system.cpu.executeFuncUnits.funcUnits4.timings.opClasses", - "type": "MinorOpClassSet" - }, - "cxx_class": "MinorFUTiming", - "path": "system.cpu.executeFuncUnits.funcUnits4.timings", - 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"opClass": "InstPrefetch", - "name": "opClasses1", - "eventq_index": 0, - "cxx_class": "MinorOpClass", - "path": "system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1", - "type": "MinorOpClass" - } - ], - "eventq_index": 0, - "cxx_class": "MinorOpClassSet", - "path": "system.cpu.executeFuncUnits.funcUnits6.opClasses", - "type": "MinorOpClassSet" - }, - "eventq_index": 0, - "timings": [], - "cxx_class": "MinorFU", - "path": "system.cpu.executeFuncUnits.funcUnits6", - "type": "MinorFU" - } - ], - "type": "MinorFUPool" - }, - "switched_out": false, - "max_insts_all_threads": 0, - "dstage2_mmu": { - "name": "dstage2_mmu", - "tlb": "system.cpu.dtb", - "sys": "system", - "stage2_tlb": { - "name": "stage2_tlb", - "is_stage2": true, - "eventq_index": 0, - "cxx_class": "ArmISA::TLB", - "walker": { - "name": "walker", - "is_stage2": true, - "clk_domain": "system.clk_domain", - "sys": "system", - "eventq_index": 0, - "cxx_class": "ArmISA::TableWalker", - "path": "system.cpu.dstage2_mmu.stage2_tlb.walker", - "type": "ArmTableWalker", - "num_squash_per_cycle": 2 - }, - "path": "system.cpu.dstage2_mmu.stage2_tlb", - "type": "ArmTLB", - "size": 32 - }, - "eventq_index": 0, - "cxx_class": "ArmISA::Stage2MMU", - "path": "system.cpu.dstage2_mmu", - "type": "ArmStage2MMU" - }, - "fetch2InputBufferSize": 2, - "profile": 0, - "fetch2ToDecodeForwardDelay": 1, - "executeInputWidth": 2, - "decodeToExecuteForwardDelay": 1, - "executeLSQRequestsQueueSize": 1, - "fetch2CycleInput": true, - "executeMaxAccessesInMemory": 2, - "enableIdling": true, - "executeLSQStoreBufferSize": 5, - "workload": [ - { - "uid": 100, - "pid": 100, - "kvmInSE": false, - "cxx_class": "LiveProcess", - "executable": "", - "drivers": [], - "system": "system", - "gid": 100, - "eventq_index": 0, - "env": [], - "input": "cin", - "ppid": 99, - "type": "LiveProcess", - "cwd": "", - "simpoint": 0, - "euid": 100, - "path": "system.cpu.workload", - "max_stack_size": 67108864, - "name": "workload", - "cmd": [ - "/home/vagrant/advanced_computer_architecture/exercises/blatt01/exec/automotive/basicmath/basicmath_small" - ], - "errout": "cerr", - "useArchPT": false, - "egid": 100, - "output": "cout" - } - ], - "name": "cpu", - "executeSetTraceTimeOnIssue": false, - "dtb": { - "name": "dtb", - "is_stage2": false, - "eventq_index": 0, - "cxx_class": "ArmISA::TLB", - "walker": { - "name": "walker", - "is_stage2": false, - "clk_domain": "system.clk_domain", - "sys": "system", - "eventq_index": 0, - "cxx_class": "ArmISA::TableWalker", - "path": "system.cpu.dtb.walker", - "type": "ArmTableWalker", - "num_squash_per_cycle": 2 - }, - "path": "system.cpu.dtb", - "type": "ArmTLB", - "size": 64 - }, - "simpoint_start_insts": [], - "executeSetTraceTimeOnCommit": true, - "tracer": { - "eventq_index": 0, - "path": "system.cpu.tracer", - "type": "ExeTracer", - "name": "tracer", - "cxx_class": "Trace::ExeTracer" - }, - "executeCommitLimit": 2, - "fetch1LineWidth": 0, - "branchPred": { - "choiceCtrBits": 2, - "name": "branchPred", - "globalCtrBits": 2, - "numThreads": 1, - "localHistoryTableSize": 2048, - "choicePredictorSize": 8192, - "instShiftAmt": 2, - "localCtrBits": 2, - "eventq_index": 0, - "BTBTagSize": 16, - "BTBEntries": 4096, - "cxx_class": "TournamentBP", - "path": "system.cpu.branchPred", - "localPredictorSize": 2048, - "type": "TournamentBP", - "RASSize": 16, - "globalPredictorSize": 8192 - }, - "path": "system.cpu", - "fetch1ToFetch2ForwardDelay": 1, - "decodeInputBufferSize": 3 - }, - "multi_thread": false, - "exit_on_work_items": false, - "work_item_id": -1, - "num_work_ids": 16 - }, - "time_sync_period": 100000000000, - "eventq_index": 0, - "time_sync_spin_threshold": 100000000, - "cxx_class": "Root", - "path": "root", - "time_sync_enable": false, - "type": "Root", - "full_system": false -} \ No newline at end of file diff --git a/aufgaben/blatt01/m5out-automotive-MinorCPU/stats.txt b/aufgaben/blatt01/m5out-automotive-MinorCPU/stats.txt deleted file mode 100644 index 1356e34..0000000 --- a/aufgaben/blatt01/m5out-automotive-MinorCPU/stats.txt +++ /dev/null @@ -1,442 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.143693 # Number of seconds simulated -sim_ticks 143692679000 # Number of ticks simulated -final_tick 143692679000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 132939 # Simulator instruction rate (inst/s) -host_op_rate 170321 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2352941458 # Simulator tick rate (ticks/s) -host_mem_usage 649496 # Number of bytes of host memory used -host_seconds 61.07 # Real time elapsed on the host -sim_insts 8118511 # Number of instructions simulated -sim_ops 10401387 # Number of ops (including micro ops) simulated -system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.bytes_read::cpu.inst 143227520 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::cpu.data 9983220 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::total 153210740 # Number of bytes read from this memory -system.mem_ctrl.bytes_inst_read::cpu.inst 143227520 # Number of instructions bytes read from this memory -system.mem_ctrl.bytes_inst_read::total 143227520 # Number of instructions bytes read from this memory -system.mem_ctrl.bytes_written::cpu.data 5724409 # Number of bytes written to this memory -system.mem_ctrl.bytes_written::total 5724409 # Number of bytes written to this memory -system.mem_ctrl.num_reads::cpu.inst 2237930 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::cpu.data 1712364 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::total 3950294 # Number of read requests responded to by this memory -system.mem_ctrl.num_writes::cpu.data 1394365 # Number of write requests responded to by this memory -system.mem_ctrl.num_writes::total 1394365 # Number of write requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 996762820 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 69476191 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 1066239011 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 996762820 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 996762820 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::cpu.data 39837861 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::total 39837861 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 996762820 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 109314052 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 1106076873 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.readReqs 3950295 # Number of read requests accepted -system.mem_ctrl.writeReqs 1394365 # Number of write requests accepted -system.mem_ctrl.readBursts 3950295 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrl.writeBursts 1394365 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 247853312 # Total number of bytes read from DRAM -system.mem_ctrl.bytesReadWrQ 4965568 # Total number of bytes read from write queue -system.mem_ctrl.bytesWritten 4096 # Total number of bytes written to DRAM -system.mem_ctrl.bytesReadSys 153210804 # Total read bytes from the system interface side -system.mem_ctrl.bytesWrittenSys 5724409 # Total written bytes from the system interface side -system.mem_ctrl.servicedByWrQ 77587 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrl.mergedWrBursts 1394276 # Number of DRAM write bursts merged with an existing one -system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrl.perBankRdBursts::0 1562452 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::1 287420 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::2 98288 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::3 755555 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::4 716034 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::5 147254 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::6 187286 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::7 12 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::8 26092 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::9 6252 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::10 3864 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::11 4313 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::12 29557 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::13 22787 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::14 16121 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::15 9421 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::0 5 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::1 2 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::2 9 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::14 3 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::15 45 # Per bank write bursts -system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 143692675000 # Total gap between requests -system.mem_ctrl.readPktSize::0 96 # Read request sizes (log2) -system.mem_ctrl.readPktSize::1 2 # Read request sizes (log2) -system.mem_ctrl.readPktSize::2 928752 # Read request sizes (log2) -system.mem_ctrl.readPktSize::3 783514 # Read request sizes (log2) -system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::6 2237931 # Read request sizes (log2) -system.mem_ctrl.writePktSize::0 5 # Write request sizes (log2) -system.mem_ctrl.writePktSize::1 2 # Write request sizes (log2) -system.mem_ctrl.writePktSize::2 1357616 # Write request sizes (log2) -system.mem_ctrl.writePktSize::3 36742 # Write request sizes (log2) -system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrl.rdQLenPdf::0 2441466 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::1 1010435 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::2 420807 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see 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-system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see 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incoming req see -system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 604698 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 409.881084 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 243.515104 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 372.649397 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 171653 28.39% 28.39% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 114542 18.94% 47.33% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 70584 11.67% 59.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 39573 6.54% 65.55% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 21829 3.61% 69.16% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 40018 6.62% 75.77% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 11989 1.98% 77.76% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-1023 21044 3.48% 81.24% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 113466 18.76% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 604698 # Bytes accessed per row activation -system.mem_ctrl.rdPerTurnAround::samples 4 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::mean 541.500000 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::gmean 473.921329 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::stdev 295.285737 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::192-223 1 25.00% 25.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::352-383 1 25.00% 50.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::704-735 1 25.00% 75.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::832-863 1 25.00% 100.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::total 4 # Reads before turning the bus around for writes -system.mem_ctrl.wrPerTurnAround::samples 4 # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::16 4 100.00% 100.00% # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::total 4 # Writes before turning the bus around for reads -system.mem_ctrl.totQLat 30576652750 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 103189927750 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 19363540000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 7895.42 # Average queueing delay per DRAM burst -system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 26645.42 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 1724.88 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 0.03 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 1066.24 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 39.84 # Average system write bandwidth in MiByte/s -system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 13.48 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 13.48 # Data bus utilization in percentage for reads -system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.mem_ctrl.avgRdQLen 1.49 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 18.00 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 3268008 # Number of row buffer hits during reads -system.mem_ctrl.writeRowHits 60 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 84.39 # Row buffer hit rate for reads -system.mem_ctrl.writeRowHitRate 67.42 # Row buffer hit rate for writes -system.mem_ctrl.avgGap 26885.28 # Average gap between requests -system.mem_ctrl.pageHitRate 84.39 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 4270916160 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 2330361000 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 29283446400 # Energy for read commands per rank (pJ) -system.mem_ctrl_0.writeEnergy 103680 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 9384966240 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 97707010275 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 504726750 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 143481530505 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 998.565034 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 126869250 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 4798040000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 138762822000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrl_1.actEnergy 300540240 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 163985250 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 922513800 # Energy for read commands per rank (pJ) -system.mem_ctrl_1.writeEnergy 311040 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 9384966240 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 61400760525 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 32352314250 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 104525391345 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 727.448338 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 53410712250 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 4798040000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 85478979000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 1212830 # Number of BP lookups -system.cpu.branchPred.condPredicted 646713 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 66330 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 833609 # Number of BTB lookups -system.cpu.branchPred.BTBHits 555956 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 66.692658 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 284936 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 59968 # Number of incorrect RAS predictions. -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.numCycles 143692679 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 8118511 # Number of instructions committed -system.cpu.committedOps 10401387 # Number of ops (including micro ops) committed -system.cpu.discardedOps 383646 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 17.699388 # CPI: cycles per instruction -system.cpu.ipc 0.056499 # IPC: instructions per cycle -system.cpu.tickCycles 28651792 # Number of cycles that the object actually ticked -system.cpu.idleCycles 115040887 # Total number of cycles that the object has spent stopped -system.membus.trans_dist::ReadReq 3950263 # Transaction distribution -system.membus.trans_dist::ReadResp 3950273 # Transaction distribution -system.membus.trans_dist::WriteReq 1394354 # Transaction distribution -system.membus.trans_dist::WriteResp 1394352 # Transaction distribution -system.membus.trans_dist::SoftPFReq 21 # Transaction distribution -system.membus.trans_dist::SoftPFResp 21 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution -system.membus.trans_dist::StoreCondReq 11 # Transaction distribution -system.membus.trans_dist::StoreCondResp 11 # Transaction distribution -system.membus.pkt_count_system.cpu.fetch1.icache_port::system.mem_ctrl.port 4475861 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.execute.dcache_port::system.mem_ctrl.port 6213456 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10689317 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.fetch1.icache_port::system.mem_ctrl.port 143227520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.execute.dcache_port::system.mem_ctrl.port 15707629 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 158935149 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 5344660 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5344660 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5344660 # Request fanout histogram -system.membus.reqLayer0.occupancy 6739025000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 4.7 # Layer utilization (%) -system.membus.respLayer0.occupancy 11833386750 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 8.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 5399315758 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 3.8 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/aufgaben/blatt01/m5out-automotive-TimingSimpleCPU/config.ini b/aufgaben/blatt01/m5out-automotive-TimingSimpleCPU/config.ini deleted file mode 100644 index 89499fa..0000000 --- a/aufgaben/blatt01/m5out-automotive-TimingSimpleCPU/config.ini +++ /dev/null @@ -1,331 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu dvfs_handler mem_ctrl membus -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges=0:536870911 -memories=system.mem_ctrl -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -readfile= -symbolfile= -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[2] - -[system.clk_domain] -type=SrcClockDomain -children=voltage_domain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.clk_domain.voltage_domain - -[system.clk_domain.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - -[system.cpu] -type=TimingSimpleCPU -children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload -branchPred=Null -checker=Null -clk_domain=system.clk_domain -cpu_id=-1 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu.dstage2_mmu -dtb=system.cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -istage2_mmu=system.cpu.istage2_mmu -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.membus.slave[1] -icache_port=system.membus.slave[0] - -[system.cpu.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.dtb - -[system.cpu.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.dstage2_mmu.stage2_tlb.walker - -[system.cpu.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -sys=system - -[system.cpu.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.dtb.walker - -[system.cpu.dtb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -sys=system - -[system.cpu.interrupts] -type=ArmInterrupts -eventq_index=0 - -[system.cpu.isa] -type=ArmISA -decoderFlavour=Generic -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 -id_aa64pfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 -midr=1091551472 -pmu=Null -system=system - -[system.cpu.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.istage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.itb - -[system.cpu.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.istage2_mmu.stage2_tlb.walker - -[system.cpu.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -sys=system - -[system.cpu.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.itb.walker - -[system.cpu.itb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -sys=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=/home/vagrant/advanced_computer_architecture/exercises/blatt01/exec/automotive/basicmath/basicmath_small -cwd= -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable= -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.mem_ctrl] -type=DRAMCtrl -IDD0=0.075000 -IDD02=0.000000 -IDD2N=0.050000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.000000 -IDD2P12=0.000000 -IDD3N=0.057000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.000000 -IDD3P12=0.000000 -IDD4R=0.187000 -IDD4R2=0.000000 -IDD4W=0.165000 -IDD4W2=0.000000 -IDD5=0.220000 -IDD52=0.000000 -IDD6=0.000000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -page_policy=open_adaptive -range=0:536870911 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=0 -tXPDLL=0 -tXS=0 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.membus] -type=CoherentXBar -clk_domain=system.clk_domain -eventq_index=0 -forward_latency=4 -frontend_latency=3 -response_latency=2 -snoop_filter=Null -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.mem_ctrl.port -slave=system.cpu.icache_port system.cpu.dcache_port system.system_port - diff --git a/aufgaben/blatt01/m5out-automotive-TimingSimpleCPU/config.json b/aufgaben/blatt01/m5out-automotive-TimingSimpleCPU/config.json deleted file mode 100644 index 7d144ba..0000000 --- a/aufgaben/blatt01/m5out-automotive-TimingSimpleCPU/config.json +++ /dev/null @@ -1,411 +0,0 @@ -{ - "name": null, - "sim_quantum": 0, - "system": { - "kernel": "", - "mmap_using_noreserve": false, - "kernel_addr_check": true, - "membus": { - "slave": { - "peer": [ - "system.cpu.icache_port", - "system.cpu.dcache_port", - "system.system_port" - ], - "role": "SLAVE" - }, - "name": "membus", - "snoop_filter": null, - "forward_latency": 4, - "clk_domain": "system.clk_domain", - "system": "system", - "width": 16, - "eventq_index": 0, - "master": { - "peer": [ - "system.mem_ctrl.port" - ], - "role": "MASTER" - }, - "response_latency": 2, - "cxx_class": "CoherentXBar", - "path": "system.membus", - "snoop_response_latency": 4, - "type": "CoherentXBar", - "use_default_range": false, - "frontend_latency": 3 - }, - "symbolfile": "", - "readfile": "", - "cxx_class": "System", - "load_offset": 0, - "work_end_ckpt_count": 0, - "memories": [ - "system.mem_ctrl" - ], - "work_begin_ckpt_count": 0, - "clk_domain": { - "name": "clk_domain", - "clock": [ - 1000 - ], - "init_perf_level": 0, - "voltage_domain": { - "name": "voltage_domain", - "eventq_index": 0, - "voltage": [ - "1.0" - ], - "cxx_class": "VoltageDomain", - "path": "system.clk_domain.voltage_domain", - "type": "VoltageDomain" - }, - "eventq_index": 0, - "cxx_class": "SrcClockDomain", - "path": "system.clk_domain", - "type": "SrcClockDomain", - "domain_id": -1 - }, - "mem_ranges": [ - "0:536870911" - ], - "eventq_index": 0, - "work_begin_cpu_id_exit": -1, - "dvfs_handler": { - "enable": false, - "name": "dvfs_handler", - "sys_clk_domain": "system.clk_domain", - "transition_latency": 100000000, - "eventq_index": 0, - "cxx_class": "DVFSHandler", - "domains": [], - "path": "system.dvfs_handler", - "type": "DVFSHandler" - }, - "work_end_exit_count": 0, - "type": "System", - "cache_line_size": 64, - "boot_osflags": "a", - "mem_ctrl": { - "static_frontend_latency": 10000, - "tRFC": 260000, - "activation_limit": 4, - "in_addr_map": true, - "IDD3N2": "0.0", - "tWTR": 7500, - "IDD52": "0.0", - "clk_domain": "system.clk_domain", - "channels": 1, - "write_buffer_size": 64, - "device_bus_width": 8, - "VDD": "1.5", - "write_high_thresh_perc": 85, - "cxx_class": "DRAMCtrl", - "bank_groups_per_rank": 0, - "IDD2N2": "0.0", - "port": { - "peer": "system.membus.master[0]", - "role": "SLAVE" - }, - "tCCD_L": 0, - "IDD2N": "0.05", - "null": false, - "IDD2P1": "0.0", - "eventq_index": 0, - "tRRD": 6000, - "tRTW": 2500, - "IDD4R": "0.187", - "burst_length": 8, - "tRTP": 7500, - "IDD4W": "0.165", - "tWR": 15000, - "banks_per_rank": 8, - "devices_per_rank": 8, - "IDD2P02": "0.0", - "IDD6": "0.0", - "IDD5": "0.22", - "tRCD": 13750, - "type": "DRAMCtrl", - "IDD3P02": "0.0", - "IDD0": "0.075", - "IDD62": "0.0", - "min_writes_per_switch": 16, - "mem_sched_policy": "frfcfs", - "IDD02": "0.0", - "IDD2P0": "0.0", - "ranks_per_channel": 2, - "page_policy": "open_adaptive", - "IDD4W2": "0.0", - "tCS": 2500, - "tCL": 13750, - "read_buffer_size": 32, - "conf_table_reported": true, - "tCK": 1250, - "tRAS": 35000, - "tRP": 13750, - "tBURST": 5000, - "path": "system.mem_ctrl", - "tXP": 0, - "tXS": 0, - "addr_mapping": "RoRaBaCoCh", - "IDD3P0": "0.0", - "IDD3P1": "0.0", - "IDD3N": "0.057", - "name": "mem_ctrl", - "tXSDLL": 0, - "device_size": 536870912, - "dll": true, - "tXAW": 30000, - "write_low_thresh_perc": 50, - "range": "0:536870911", - "VDD2": "0.0", - "IDD2P12": "0.0", - "tRRD_L": 0, - "tXPDLL": 0, - "IDD4R2": "0.0", - "device_rowbuffer_size": 1024, - "static_backend_latency": 10000, - "max_accesses_per_row": 16, - "IDD3P12": "0.0", - "tREFI": 7800000 - }, - "work_cpus_ckpt_count": 0, - "work_begin_exit_count": 0, - "path": "system", - "mem_mode": "timing", - "name": "system", - "init_param": 0, - "system_port": { - "peer": "system.membus.slave[2]", - "role": "MASTER" - }, - "load_addr_mask": 1099511627775, - "cpu": { - "do_statistics_insts": true, - "numThreads": 1, - "itb": { - "name": "itb", - "is_stage2": false, - "eventq_index": 0, - "cxx_class": "ArmISA::TLB", - "walker": { - "name": "walker", - "is_stage2": false, - "clk_domain": "system.clk_domain", - "sys": "system", - "eventq_index": 0, - "cxx_class": "ArmISA::TableWalker", - "path": "system.cpu.itb.walker", - "type": "ArmTableWalker", - "num_squash_per_cycle": 2 - }, - "path": "system.cpu.itb", - "type": "ArmTLB", - "size": 64 - }, - "system": "system", - "istage2_mmu": { - "name": "istage2_mmu", - "tlb": "system.cpu.itb", - "sys": "system", - "stage2_tlb": { - "name": "stage2_tlb", - "is_stage2": true, - "eventq_index": 0, - "cxx_class": "ArmISA::TLB", - "walker": { - "name": "walker", - "is_stage2": true, - "clk_domain": "system.clk_domain", - "sys": "system", - "eventq_index": 0, - "cxx_class": "ArmISA::TableWalker", - "path": "system.cpu.istage2_mmu.stage2_tlb.walker", - "type": "ArmTableWalker", - "num_squash_per_cycle": 2 - }, - "path": "system.cpu.istage2_mmu.stage2_tlb", - "type": "ArmTLB", - "size": 32 - }, - "eventq_index": 0, - "cxx_class": "ArmISA::Stage2MMU", - "path": "system.cpu.istage2_mmu", - "type": "ArmStage2MMU" - }, - "function_trace": false, - "do_checkpoint_insts": true, - "cxx_class": "TimingSimpleCPU", - "max_loads_all_threads": 0, - "clk_domain": "system.clk_domain", - "function_trace_start": 0, - "cpu_id": -1, - "checker": null, - "eventq_index": 0, - "do_quiesce": true, - "type": "TimingSimpleCPU", - "profile": 0, - "icache_port": { - "peer": "system.membus.slave[0]", - "role": "MASTER" - }, - "interrupts": [ - { - "eventq_index": 0, - "path": "system.cpu.interrupts", - "type": "ArmInterrupts", - "name": "interrupts", - "cxx_class": "ArmISA::Interrupts" - } - ], - "dcache_port": { - "peer": "system.membus.slave[1]", - "role": "MASTER" - }, - "socket_id": 0, - "max_insts_all_threads": 0, - "dstage2_mmu": { - "name": "dstage2_mmu", - "tlb": "system.cpu.dtb", - "sys": "system", - "stage2_tlb": { - "name": "stage2_tlb", - "is_stage2": true, - "eventq_index": 0, - "cxx_class": "ArmISA::TLB", - "walker": { - "name": "walker", - "is_stage2": true, - "clk_domain": "system.clk_domain", - "sys": "system", - "eventq_index": 0, - "cxx_class": "ArmISA::TableWalker", - "path": "system.cpu.dstage2_mmu.stage2_tlb.walker", - "type": "ArmTableWalker", - "num_squash_per_cycle": 2 - }, - "path": "system.cpu.dstage2_mmu.stage2_tlb", - "type": "ArmTLB", - "size": 32 - }, - "eventq_index": 0, - "cxx_class": "ArmISA::Stage2MMU", - "path": "system.cpu.dstage2_mmu", - "type": "ArmStage2MMU" - }, - "path": "system.cpu", - "max_loads_any_thread": 0, - "switched_out": false, - "workload": [ - { - "uid": 100, - "pid": 100, - "kvmInSE": false, - "cxx_class": "LiveProcess", - "executable": "", - "drivers": [], - "system": "system", - "gid": 100, - "eventq_index": 0, - "env": [], - "input": "cin", - "ppid": 99, - "type": "LiveProcess", - "cwd": "", - "simpoint": 0, - "euid": 100, - "path": "system.cpu.workload", - "max_stack_size": 67108864, - "name": "workload", - "cmd": [ - "/home/vagrant/advanced_computer_architecture/exercises/blatt01/exec/automotive/basicmath/basicmath_small" - ], - "errout": "cerr", - "useArchPT": false, - "egid": 100, - "output": "cout" - } - ], - "name": "cpu", - "dtb": { - "name": "dtb", - "is_stage2": false, - "eventq_index": 0, - "cxx_class": "ArmISA::TLB", - "walker": { - "name": "walker", - "is_stage2": false, - "clk_domain": "system.clk_domain", - "sys": "system", - "eventq_index": 0, - "cxx_class": "ArmISA::TableWalker", - "path": "system.cpu.dtb.walker", - "type": "ArmTableWalker", - "num_squash_per_cycle": 2 - }, - "path": "system.cpu.dtb", - "type": "ArmTLB", - "size": 64 - }, - "simpoint_start_insts": [], - "max_insts_any_thread": 0, - "progress_interval": 0, - "branchPred": null, - "isa": [ - { - "pmu": null, - "id_pfr1": 4113, - "id_pfr0": 49, - "id_isar1": 34677009, - "id_isar0": 34607377, - "id_isar3": 17899825, - "id_isar2": 555950401, - "id_isar5": 0, - "id_isar4": 268501314, - "cxx_class": "ArmISA::ISA", - "id_aa64mmfr1_el1": 0, - "id_aa64pfr1_el1": 0, - "system": "system", - "eventq_index": 0, - "type": "ArmISA", - "id_aa64dfr1_el1": 0, - "fpsid": 1090793632, - "id_mmfr0": 270536963, - "id_mmfr1": 0, - "id_mmfr2": 19070976, - "id_mmfr3": 34611729, - "id_aa64mmfr0_el1": 15728642, - "id_aa64dfr0_el1": 1052678, - "path": "system.cpu.isa", - "id_aa64isar0_el1": 0, - "decoderFlavour": "Generic", - "name": "isa", - "midr": 1091551472, - "id_aa64afr0_el1": 0, - "id_aa64isar1_el1": 0, - "id_aa64afr1_el1": 0, - "id_aa64pfr0_el1": 17 - } - ], - "tracer": { - "eventq_index": 0, - "path": "system.cpu.tracer", - "type": "ExeTracer", - "name": "tracer", - "cxx_class": "Trace::ExeTracer" - } - }, - "multi_thread": false, - "exit_on_work_items": false, - "work_item_id": -1, - "num_work_ids": 16 - }, - "time_sync_period": 100000000000, - "eventq_index": 0, - "time_sync_spin_threshold": 100000000, - "cxx_class": "Root", - "path": "root", - "time_sync_enable": false, - "type": "Root", - "full_system": false -} \ No newline at end of file diff --git a/aufgaben/blatt01/m5out-automotive-TimingSimpleCPU/stats.txt b/aufgaben/blatt01/m5out-automotive-TimingSimpleCPU/stats.txt deleted file mode 100644 index 949802a..0000000 --- a/aufgaben/blatt01/m5out-automotive-TimingSimpleCPU/stats.txt +++ /dev/null @@ -1,481 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.702617 # Number of seconds simulated -sim_ticks 702617073000 # Number of ticks simulated -final_tick 702617073000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 284164 # Simulator instruction rate (inst/s) -host_op_rate 364069 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 24593023532 # Simulator tick rate (ticks/s) -host_mem_usage 648216 # Number of bytes of host memory used -host_seconds 28.57 # Real time elapsed on the host -sim_insts 8118483 # Number of instructions simulated -sim_ops 10401348 # Number of ops (including micro ops) simulated -system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.bytes_read::cpu.inst 46241516 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::cpu.data 9897865 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::total 56139381 # Number of bytes read from this memory -system.mem_ctrl.bytes_inst_read::cpu.inst 46241516 # Number of instructions bytes read from this memory -system.mem_ctrl.bytes_inst_read::total 46241516 # Number of instructions bytes read from this memory -system.mem_ctrl.bytes_written::cpu.data 5724409 # Number of bytes written to this memory -system.mem_ctrl.bytes_written::total 5724409 # Number of bytes written to this memory -system.mem_ctrl.num_reads::cpu.inst 11560379 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::cpu.data 1702140 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::total 13262519 # Number of read requests responded to by this memory -system.mem_ctrl.num_writes::cpu.data 1394365 # Number of write requests responded to by this memory -system.mem_ctrl.num_writes::total 1394365 # Number of write requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 65813254 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 14087140 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 79900394 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 65813254 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 65813254 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::cpu.data 8147267 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::total 8147267 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 65813254 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 22234407 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 88047661 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.readReqs 13262520 # Number of read requests accepted -system.mem_ctrl.writeReqs 1394365 # Number of write requests accepted -system.mem_ctrl.readBursts 13262520 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrl.writeBursts 1394365 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 844215104 # Total number of bytes read from DRAM -system.mem_ctrl.bytesReadWrQ 4586176 # Total number of bytes read from write queue -system.mem_ctrl.bytesWritten 5120 # Total number of bytes written to DRAM -system.mem_ctrl.bytesReadSys 56139385 # Total read bytes from the system interface side -system.mem_ctrl.bytesWrittenSys 5724409 # Total written bytes from the system interface side -system.mem_ctrl.servicedByWrQ 71659 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrl.mergedWrBursts 1394263 # Number of DRAM write bursts merged with an existing one -system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrl.perBankRdBursts::0 3387002 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::1 843189 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::2 99860 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::3 1479473 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::4 4117858 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::5 844983 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::6 2296781 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::7 28 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::8 26317 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::9 6247 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::10 4833 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::11 5007 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::12 29993 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::13 23147 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::14 16344 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::15 9799 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::0 20 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::1 9 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::2 9 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::14 3 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::15 39 # Per bank write bursts -system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 702616997000 # Total gap between requests -system.mem_ctrl.readPktSize::0 91 # Read request sizes (log2) -system.mem_ctrl.readPktSize::1 1 # Read request sizes (log2) -system.mem_ctrl.readPktSize::2 12490033 # Read request sizes (log2) -system.mem_ctrl.readPktSize::3 772395 # Read request sizes (log2) -system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::6 0 # Read request sizes (log2) -system.mem_ctrl.writePktSize::0 5 # Write request sizes (log2) -system.mem_ctrl.writePktSize::1 2 # Write request sizes (log2) -system.mem_ctrl.writePktSize::2 1357616 # Write request sizes (log2) -system.mem_ctrl.writePktSize::3 36742 # Write request sizes (log2) -system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrl.rdQLenPdf::0 13190855 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::1 6 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::15 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::16 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::17 6 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::18 6 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::19 6 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::20 6 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::21 6 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::22 5 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::23 5 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::24 5 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::25 5 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::26 5 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::27 5 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::28 5 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::29 5 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::30 5 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::31 5 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::32 5 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 1163485 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 725.594874 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 544.779437 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 376.356111 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 112777 9.69% 9.69% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 98796 8.49% 18.18% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 96776 8.32% 26.50% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 46399 3.99% 30.49% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 51545 4.43% 34.92% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 55885 4.80% 39.72% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 30477 2.62% 42.34% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-1023 37964 3.26% 45.61% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 632866 54.39% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 1163485 # Bytes accessed per row activation -system.mem_ctrl.rdPerTurnAround::samples 5 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::mean 2638125 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::gmean 7777.289718 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::stdev 5896019.911261 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::0-524287 4 80.00% 80.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1.31072e+07-1.36315e+07 1 20.00% 100.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::total 5 # Reads before turning the bus around for writes -system.mem_ctrl.wrPerTurnAround::samples 5 # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::16 5 100.00% 100.00% # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::total 5 # Writes before turning the bus around for reads -system.mem_ctrl.totQLat 39894506750 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 287223150500 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 65954305000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 3024.41 # Average queueing delay per DRAM burst -system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 21774.41 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 1201.53 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 0.01 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 79.90 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 8.15 # Average system write bandwidth in MiByte/s -system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 9.39 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 9.39 # Data bus utilization in percentage for reads -system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 30.93 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 12027385 # Number of row buffer hits during reads -system.mem_ctrl.writeRowHits 67 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 91.18 # Row buffer hit rate for reads -system.mem_ctrl.writeRowHitRate 65.69 # Row buffer hit rate for writes -system.mem_ctrl.avgGap 47937.68 # Average gap between requests -system.mem_ctrl.pageHitRate 91.18 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 8430806160 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 4600142250 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 101939518200 # Energy for read commands per rank (pJ) -system.mem_ctrl_0.writeEnergy 246240 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 45891437280 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 474579027450 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 5272140000 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 640713317580 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 911.896997 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 4383705250 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 23461880000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 674770316000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrl_1.actEnergy 365140440 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 199233375 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 949018200 # Energy for read commands per rank (pJ) -system.mem_ctrl_1.writeEnergy 272160 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 45891437280 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 134521471170 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 303568242000 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 485494814625 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 690.981834 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 504147571500 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 23461880000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 175006511500 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.numCycles 702617073 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 8118483 # Number of instructions committed -system.cpu.committedOps 10401348 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 7068256 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 4980727 # Number of float alu accesses -system.cpu.num_func_calls 387874 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 546862 # number of instructions that are conditional controls -system.cpu.num_int_insts 7068256 # number of integer instructions -system.cpu.num_fp_insts 4980727 # number of float instructions -system.cpu.num_int_register_reads 42369898 # number of times the integer registers were read -system.cpu.num_int_register_writes 5749679 # number of times the integer registers were written -system.cpu.num_fp_register_reads 9978213 # number of times the floating registers were read -system.cpu.num_fp_register_writes 6615333 # number of times the floating registers were written -system.cpu.num_cc_register_reads 36480319 # number of times the CC registers were read -system.cpu.num_cc_register_writes 2736302 # number of times the CC registers were written -system.cpu.num_mem_refs 3096528 # number of memory refs -system.cpu.num_load_insts 1702147 # Number of load instructions -system.cpu.num_store_insts 1394381 # Number of store instructions -system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 702617072.999000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 978284 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 4356627 41.89% 41.89% # Class of executed instruction -system.cpu.op_class::IntMult 4 0.00% 41.89% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 41.89% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 41.89% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 41.89% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 41.89% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 41.89% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 41.89% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 41.89% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 41.89% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 41.89% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 41.89% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 41.89% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 41.89% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 41.89% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 41.89% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 41.89% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 41.89% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 41.89% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 41.89% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 732413 7.04% 48.93% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 48.93% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 172095 1.65% 50.58% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 50.58% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 149013 1.43% 52.01% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 1092367 10.50% 62.52% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 349482 3.36% 65.88% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 433860 4.17% 70.05% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 18998 0.18% 70.23% # Class of executed instruction -system.cpu.op_class::MemRead 1702147 16.36% 86.59% # Class of executed instruction -system.cpu.op_class::MemWrite 1394381 13.41% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 10401387 # Class of executed instruction -system.membus.trans_dist::ReadReq 13262488 # Transaction distribution -system.membus.trans_dist::ReadResp 13262498 # Transaction distribution -system.membus.trans_dist::WriteReq 1394354 # Transaction distribution -system.membus.trans_dist::WriteResp 1394354 # Transaction distribution -system.membus.trans_dist::SoftPFReq 21 # Transaction distribution -system.membus.trans_dist::SoftPFResp 21 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution -system.membus.trans_dist::StoreCondReq 11 # Transaction distribution -system.membus.trans_dist::StoreCondResp 11 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 23120759 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 6193010 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 29313769 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 46241516 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 15622274 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 61863790 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 14656885 # Request fanout histogram -system.membus.snoop_fanout::mean 0.788734 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.408207 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3096505 21.13% 21.13% # Request fanout histogram -system.membus.snoop_fanout::1 11560380 78.87% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 14656885 # Request fanout histogram -system.membus.reqLayer0.occupancy 16051250000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.membus.respLayer0.occupancy 26241570250 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 5288313000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.8 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/aufgaben/blatt01/m5out/config.ini b/aufgaben/blatt01/m5out/config.ini deleted file mode 100644 index e6591b3..0000000 --- a/aufgaben/blatt01/m5out/config.ini +++ /dev/null @@ -1,930 +0,0 @@ -[root] -type=Root -children=switch_cpu system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[switch_cpu] -type=TimingSimpleCPU -children=clk_domain dstage2_mmu dtb interrupts isa istage2_mmu itb tracer -branchPred=Null -checker=Null -clk_domain=switch_cpu.clk_domain -cpu_id=-1 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=switch_cpu.dstage2_mmu -dtb=switch_cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=switch_cpu.interrupts -isa=switch_cpu.isa -istage2_mmu=switch_cpu.istage2_mmu -itb=switch_cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=true -system=system -tracer=switch_cpu.tracer -workload=system.cpu.workload -dcache_port=system.membus.slave[3] -icache_port=system.membus.slave[2] - -[switch_cpu.clk_domain] -type=SrcClockDomain -children=voltage_domain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=switch_cpu.clk_domain.voltage_domain - -[switch_cpu.clk_domain.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - -[switch_cpu.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=switch_cpu.dstage2_mmu.stage2_tlb -sys=system -tlb=switch_cpu.dtb - -[switch_cpu.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=switch_cpu.dstage2_mmu.stage2_tlb.walker - -[switch_cpu.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=switch_cpu.clk_domain -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -sys=system - -[switch_cpu.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=switch_cpu.dtb.walker - -[switch_cpu.dtb.walker] -type=ArmTableWalker -clk_domain=switch_cpu.clk_domain -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -sys=system - -[switch_cpu.interrupts] -type=ArmInterrupts -eventq_index=0 - -[switch_cpu.isa] -type=ArmISA -decoderFlavour=Generic -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 -id_aa64pfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 -midr=1091551472 -pmu=Null -system=system - -[switch_cpu.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=switch_cpu.istage2_mmu.stage2_tlb -sys=system -tlb=switch_cpu.itb - -[switch_cpu.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=switch_cpu.istage2_mmu.stage2_tlb.walker - -[switch_cpu.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=switch_cpu.clk_domain -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -sys=system - -[switch_cpu.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=switch_cpu.itb.walker - -[switch_cpu.itb.walker] -type=ArmTableWalker -clk_domain=switch_cpu.clk_domain -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -sys=system - -[switch_cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system] -type=System -children=clk_domain cpu dvfs_handler mem_ctrl membus -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges=0:536870911 -memories=system.mem_ctrl -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -readfile= -symbolfile= -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[4] - -[system.clk_domain] -type=SrcClockDomain -children=voltage_domain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.clk_domain.voltage_domain - -[system.clk_domain.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - -[system.cpu] -type=MinorCPU -children=branchPred dstage2_mmu dtb executeFuncUnits interrupts isa istage2_mmu itb tracer workload -branchPred=system.cpu.branchPred -checker=Null -clk_domain=system.clk_domain -cpu_id=-1 -decodeCycleInput=true -decodeInputBufferSize=3 -decodeInputWidth=2 -decodeToExecuteForwardDelay=1 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu.dstage2_mmu -dtb=system.cpu.dtb -enableIdling=true -eventq_index=0 -executeAllowEarlyMemoryIssue=true -executeBranchDelay=1 -executeCommitLimit=2 -executeCycleInput=true -executeFuncUnits=system.cpu.executeFuncUnits -executeInputBufferSize=7 -executeInputWidth=2 -executeIssueLimit=2 -executeLSQMaxStoreBufferStoresPerCycle=2 -executeLSQRequestsQueueSize=1 -executeLSQStoreBufferSize=5 -executeLSQTransfersQueueSize=2 -executeMaxAccessesInMemory=2 -executeMemoryCommitLimit=1 -executeMemoryIssueLimit=1 -executeMemoryWidth=0 -executeSetTraceTimeOnCommit=true -executeSetTraceTimeOnIssue=false -fetch1FetchLimit=1 -fetch1LineSnapWidth=0 -fetch1LineWidth=0 -fetch1ToFetch2BackwardDelay=1 -fetch1ToFetch2ForwardDelay=1 -fetch2CycleInput=true -fetch2InputBufferSize=2 -fetch2ToDecodeForwardDelay=1 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -istage2_mmu=system.cpu.istage2_mmu -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.membus.slave[1] -icache_port=system.membus.slave[0] - -[system.cpu.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 - -[system.cpu.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.dtb - -[system.cpu.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.dstage2_mmu.stage2_tlb.walker - -[system.cpu.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -sys=system - -[system.cpu.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.dtb.walker - -[system.cpu.dtb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -sys=system - -[system.cpu.executeFuncUnits] -type=MinorFUPool -children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 -eventq_index=0 -funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 - -[system.cpu.executeFuncUnits.funcUnits0] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits0.timings - -[system.cpu.executeFuncUnits.funcUnits0.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits0.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits1] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits1.timings - -[system.cpu.executeFuncUnits.funcUnits1.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits1.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - 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opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] -type=MinorOpClass -eventq_index=0 -opClass=FloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] -type=MinorOpClass -eventq_index=0 -opClass=FloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] -type=MinorOpClass -eventq_index=0 -opClass=FloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] -type=MinorOpClass -eventq_index=0 -opClass=FloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] -type=MinorOpClass -eventq_index=0 -opClass=FloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] -type=MinorOpClass -eventq_index=0 -opClass=FloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] -type=MinorOpClass -eventq_index=0 -opClass=SimdAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] -type=MinorOpClass -eventq_index=0 -opClass=SimdAddAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] -type=MinorOpClass -eventq_index=0 -opClass=SimdAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] -type=MinorOpClass -eventq_index=0 -opClass=SimdCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] -type=MinorOpClass -eventq_index=0 -opClass=SimdCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] -type=MinorOpClass -eventq_index=0 -opClass=SimdMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] -type=MinorOpClass -eventq_index=0 -opClass=SimdMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] -type=MinorOpClass -eventq_index=0 -opClass=SimdMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] -type=MinorOpClass -eventq_index=0 -opClass=SimdShift - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] -type=MinorOpClass -eventq_index=0 -opClass=SimdShiftAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] -type=MinorOpClass -eventq_index=0 -opClass=SimdSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.timings] -type=MinorFUTiming -children=opClasses -description=FloatSimd -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits5] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses -opLat=1 -timings=system.cpu.executeFuncUnits.funcUnits5.timings - -[system.cpu.executeFuncUnits.funcUnits5.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=MemRead - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=MemWrite - -[system.cpu.executeFuncUnits.funcUnits5.timings] -type=MinorFUTiming -children=opClasses -description=Mem -eventq_index=0 -extraAssumedLat=2 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses -srcRegsRelativeLats=1 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits6] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses -opLat=1 -timings= - -[system.cpu.executeFuncUnits.funcUnits6.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=IprAccess - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=InstPrefetch - -[system.cpu.interrupts] -type=ArmInterrupts -eventq_index=0 - -[system.cpu.isa] -type=ArmISA -decoderFlavour=Generic -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 -id_aa64pfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 -midr=1091551472 -pmu=Null -system=system - -[system.cpu.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.istage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.itb - -[system.cpu.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.istage2_mmu.stage2_tlb.walker - -[system.cpu.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -sys=system - -[system.cpu.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.itb.walker - -[system.cpu.itb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -sys=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=/home/vagrant/advanced_computer_architecture/exercises/blatt01/exec/automotive/basicmath/basicmath_small -cwd= -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable= -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.mem_ctrl] -type=DRAMCtrl -IDD0=0.075000 -IDD02=0.000000 -IDD2N=0.050000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.000000 -IDD2P12=0.000000 -IDD3N=0.057000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.000000 -IDD3P12=0.000000 -IDD4R=0.187000 -IDD4R2=0.000000 -IDD4W=0.165000 -IDD4W2=0.000000 -IDD5=0.220000 -IDD52=0.000000 -IDD6=0.000000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -page_policy=open_adaptive -range=0:536870911 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=0 -tXPDLL=0 -tXS=0 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.membus] -type=CoherentXBar -clk_domain=system.clk_domain -eventq_index=0 -forward_latency=4 -frontend_latency=3 -point_of_coherency=true -response_latency=2 -snoop_filter=Null -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.mem_ctrl.port -slave=system.cpu.icache_port system.cpu.dcache_port switch_cpu.icache_port switch_cpu.dcache_port system.system_port - diff --git a/aufgaben/blatt01/m5out/config.json b/aufgaben/blatt01/m5out/config.json deleted file mode 100644 index bcb0afb..0000000 --- a/aufgaben/blatt01/m5out/config.json +++ /dev/null @@ -1,1222 +0,0 @@ -{ - "name": null, - "sim_quantum": 0, - "system": { - "kernel": "", - "mmap_using_noreserve": false, - "kernel_addr_check": true, - "membus": { - "slave": { - "peer": [ - "system.cpu.icache_port", - "system.cpu.dcache_port", - "switch_cpu.icache_port", - "switch_cpu.dcache_port", - "system.system_port" - ], - "role": "SLAVE" - }, - "name": "membus", - "point_of_coherency": true, - "snoop_filter": null, - "forward_latency": 4, - "clk_domain": "system.clk_domain", - "system": "system", - "width": 16, - "eventq_index": 0, - "master": { - "peer": [ - "system.mem_ctrl.port" - ], - "role": "MASTER" - }, - "response_latency": 2, - "cxx_class": "CoherentXBar", - "path": "system.membus", - "snoop_response_latency": 4, - "type": "CoherentXBar", - "use_default_range": false, - "frontend_latency": 3 - }, - "symbolfile": "", - "readfile": "", - "cxx_class": "System", - "load_offset": 0, - "work_end_ckpt_count": 0, - "memories": [ - "system.mem_ctrl" - ], - "work_begin_ckpt_count": 0, - "clk_domain": { - "name": "clk_domain", - "clock": [ - 1000 - ], - "init_perf_level": 0, - "voltage_domain": { - "name": "voltage_domain", - "eventq_index": 0, - "voltage": [ - "1.0" - ], - "cxx_class": "VoltageDomain", - "path": "system.clk_domain.voltage_domain", - "type": "VoltageDomain" - }, - "eventq_index": 0, - "cxx_class": "SrcClockDomain", - "path": "system.clk_domain", - "type": "SrcClockDomain", - "domain_id": -1 - }, - "mem_ranges": [ - "0:536870911" - ], - "eventq_index": 0, - "work_begin_cpu_id_exit": -1, - "dvfs_handler": { - "enable": false, - "name": "dvfs_handler", - "sys_clk_domain": "system.clk_domain", - "transition_latency": 100000000, - "eventq_index": 0, - "cxx_class": "DVFSHandler", - "domains": [], - "path": "system.dvfs_handler", - "type": "DVFSHandler" - }, - "work_end_exit_count": 0, - "type": "System", - "cache_line_size": 64, - "boot_osflags": "a", - "mem_ctrl": { - "static_frontend_latency": 10000, - "tRFC": 260000, - "activation_limit": 4, - "in_addr_map": true, - "IDD3N2": "0.0", - "tWTR": 7500, - "IDD52": "0.0", - "clk_domain": "system.clk_domain", - "channels": 1, - "write_buffer_size": 64, - "device_bus_width": 8, - "VDD": "1.5", - "write_high_thresh_perc": 85, - "cxx_class": "DRAMCtrl", - "bank_groups_per_rank": 0, - "IDD2N2": "0.0", - "port": { - "peer": "system.membus.master[0]", - "role": "SLAVE" - }, - "tCCD_L": 0, - "IDD2N": "0.05", - "null": false, - "IDD2P1": "0.0", - "eventq_index": 0, - "tRRD": 6000, - "tRTW": 2500, - "IDD4R": "0.187", - "burst_length": 8, - "tRTP": 7500, - "IDD4W": "0.165", - "tWR": 15000, - "banks_per_rank": 8, - "devices_per_rank": 8, - "IDD2P02": "0.0", - "IDD6": "0.0", - "IDD5": "0.22", - "tRCD": 13750, - "type": "DRAMCtrl", - "IDD3P02": "0.0", - "IDD0": "0.075", - "IDD62": "0.0", - "min_writes_per_switch": 16, - "mem_sched_policy": "frfcfs", - "IDD02": "0.0", - "IDD2P0": "0.0", - "ranks_per_channel": 2, - "page_policy": "open_adaptive", - "IDD4W2": "0.0", - "tCS": 2500, - "tCL": 13750, - "read_buffer_size": 32, - "conf_table_reported": true, - "tCK": 1250, - "tRAS": 35000, - "tRP": 13750, - "tBURST": 5000, - "path": "system.mem_ctrl", - "tXP": 0, - "tXS": 0, - "addr_mapping": "RoRaBaCoCh", - "IDD3P0": "0.0", - "IDD3P1": "0.0", - "IDD3N": "0.057", - "name": "mem_ctrl", - "tXSDLL": 0, - "device_size": 536870912, - "dll": true, - "tXAW": 30000, - "write_low_thresh_perc": 50, - "range": "0:536870911", - "VDD2": "0.0", - "IDD2P12": "0.0", - "tRRD_L": 0, - "tXPDLL": 0, - "IDD4R2": "0.0", - "device_rowbuffer_size": 1024, - "static_backend_latency": 10000, - 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- "fetch1ToFetch2ForwardDelay": 1, - "decodeInputBufferSize": 3 - }, - "multi_thread": false, - "exit_on_work_items": false, - "work_item_id": -1, - "num_work_ids": 16 - }, - "time_sync_period": 100000000000, - "eventq_index": 0, - "switch_cpu": { - "do_statistics_insts": true, - "numThreads": 1, - "itb": { - "name": "itb", - "is_stage2": false, - "eventq_index": 0, - "cxx_class": "ArmISA::TLB", - "walker": { - "name": "walker", - "is_stage2": false, - "clk_domain": "switch_cpu.clk_domain", - "sys": "system", - "eventq_index": 0, - "cxx_class": "ArmISA::TableWalker", - "path": "switch_cpu.itb.walker", - "type": "ArmTableWalker", - "num_squash_per_cycle": 2 - }, - "path": "switch_cpu.itb", - "type": "ArmTLB", - "size": 64 - }, - "system": "system", - "istage2_mmu": { - "name": "istage2_mmu", - "tlb": "switch_cpu.itb", - "sys": "system", - "stage2_tlb": { - "name": "stage2_tlb", - "is_stage2": true, - "eventq_index": 0, - "cxx_class": "ArmISA::TLB", - "walker": { - "name": "walker", - "is_stage2": true, - "clk_domain": "switch_cpu.clk_domain", - "sys": "system", - "eventq_index": 0, - "cxx_class": "ArmISA::TableWalker", - "path": "switch_cpu.istage2_mmu.stage2_tlb.walker", - "type": "ArmTableWalker", - "num_squash_per_cycle": 2 - }, - "path": "switch_cpu.istage2_mmu.stage2_tlb", - "type": "ArmTLB", - "size": 32 - }, - "eventq_index": 0, - "cxx_class": "ArmISA::Stage2MMU", - "path": "switch_cpu.istage2_mmu", - "type": "ArmStage2MMU" - }, - "function_trace": false, - "do_checkpoint_insts": true, - "cxx_class": "TimingSimpleCPU", - "max_loads_all_threads": 0, - "clk_domain": { - "name": "clk_domain", - "clock": [ - 1000 - ], - "init_perf_level": 0, - "voltage_domain": { - "name": "voltage_domain", - "eventq_index": 0, - "voltage": [ - "1.0" - ], - "cxx_class": "VoltageDomain", - "path": "switch_cpu.clk_domain.voltage_domain", - "type": "VoltageDomain" - }, - "eventq_index": 0, - "cxx_class": "SrcClockDomain", - "path": "switch_cpu.clk_domain", - "type": "SrcClockDomain", - "domain_id": -1 - }, - "function_trace_start": 0, - "cpu_id": -1, - "checker": null, - "eventq_index": 0, - "do_quiesce": true, - "type": "TimingSimpleCPU", - "profile": 0, - "icache_port": { - "peer": "system.membus.slave[2]", - "role": "MASTER" - }, - "interrupts": [ - { - "eventq_index": 0, - "path": "switch_cpu.interrupts", - "type": "ArmInterrupts", - "name": "interrupts", - "cxx_class": "ArmISA::Interrupts" - } - ], - "dcache_port": { - "peer": "system.membus.slave[3]", - "role": "MASTER" - }, - "socket_id": 0, - "max_insts_all_threads": 0, - "dstage2_mmu": { - "name": "dstage2_mmu", - "tlb": "switch_cpu.dtb", - "sys": "system", - "stage2_tlb": { - "name": "stage2_tlb", - "is_stage2": true, - "eventq_index": 0, - "cxx_class": "ArmISA::TLB", - "walker": { - "name": "walker", - "is_stage2": true, - "clk_domain": "switch_cpu.clk_domain", - "sys": "system", - "eventq_index": 0, - "cxx_class": "ArmISA::TableWalker", - "path": "switch_cpu.dstage2_mmu.stage2_tlb.walker", - "type": "ArmTableWalker", - "num_squash_per_cycle": 2 - }, - "path": "switch_cpu.dstage2_mmu.stage2_tlb", - "type": "ArmTLB", - "size": 32 - }, - "eventq_index": 0, - "cxx_class": "ArmISA::Stage2MMU", - "path": "switch_cpu.dstage2_mmu", - "type": "ArmStage2MMU" - }, - "path": "switch_cpu", - "max_loads_any_thread": 0, - "switched_out": true, - "workload": [ - "system.cpu.workload" - ], - "name": "switch_cpu", - "dtb": { - "name": "dtb", - "is_stage2": false, - "eventq_index": 0, - "cxx_class": "ArmISA::TLB", - "walker": { - "name": "walker", - "is_stage2": false, - "clk_domain": "switch_cpu.clk_domain", - "sys": "system", - "eventq_index": 0, - "cxx_class": "ArmISA::TableWalker", - "path": "switch_cpu.dtb.walker", - "type": "ArmTableWalker", - "num_squash_per_cycle": 2 - }, - "path": "switch_cpu.dtb", - "type": "ArmTLB", - "size": 64 - }, - "simpoint_start_insts": [], - "max_insts_any_thread": 0, - "progress_interval": 0, - "branchPred": null, - "isa": [ - { - "pmu": null, - "id_pfr1": 4113, - "id_pfr0": 49, - "id_isar1": 34677009, - "id_isar0": 34607377, - "id_isar3": 17899825, - "id_isar2": 555950401, - "id_isar5": 0, - "id_isar4": 268501314, - "cxx_class": "ArmISA::ISA", - "id_aa64mmfr1_el1": 0, - "id_aa64pfr1_el1": 0, - "system": "system", - "eventq_index": 0, - "type": "ArmISA", - "id_aa64dfr1_el1": 0, - "fpsid": 1090793632, - "id_mmfr0": 270536963, - "id_mmfr1": 0, - "id_mmfr2": 19070976, - "id_mmfr3": 34611729, - "id_aa64mmfr0_el1": 15728642, - "id_aa64dfr0_el1": 1052678, - "path": "switch_cpu.isa", - "id_aa64isar0_el1": 0, - "decoderFlavour": "Generic", - "name": "isa", - "midr": 1091551472, - "id_aa64afr0_el1": 0, - "id_aa64isar1_el1": 0, - "id_aa64afr1_el1": 0, - "id_aa64pfr0_el1": 17 - } - ], - "tracer": { - "eventq_index": 0, - "path": "switch_cpu.tracer", - "type": "ExeTracer", - "name": "tracer", - "cxx_class": "Trace::ExeTracer" - } - }, - "time_sync_spin_threshold": 100000000, - "cxx_class": "Root", - "path": "root", - "time_sync_enable": false, - "type": "Root", - "full_system": false -} \ No newline at end of file diff --git a/aufgaben/blatt01/m5out/stats.txt b/aufgaben/blatt01/m5out/stats.txt deleted file mode 100644 index e69de29..0000000 diff --git a/aufgaben/blatt01/simple.py b/aufgaben/blatt01/simple.py index 58a3245..2d63733 100644 --- a/aufgaben/blatt01/simple.py +++ b/aufgaben/blatt01/simple.py @@ -1,6 +1,7 @@ import m5 from m5.objects import * + system = System() system.clk_domain = SrcClockDomain() @@ -11,12 +12,28 @@ system.mem_mode = 'timing' system.mem_ranges = [AddrRange('512MB')] system.cpu = TimingSimpleCPU() +system.cpu.createInterruptController() -system.membus = CoherentBus() +system.membus = SystemXBar() system.cpu.icache_port = system.membus.slave system.cpu.dcache_port = system.membus.slave -system.mem_ctrl = DDR3_1600_x64() +system.mem_ctrl = DDR4_2400_x64() system.mem_ctrl.range = system.mem_ranges[0] system.mem_ctrl.port = system.membus.master + +process = LiveProcess() +process.cmd = ['./hello.elf'] +system.cpu.workload = process +system.cpu.createThreads() + +root = Root(full_system = False, system = system) + +m5.instantiate() + +print "Beginning simulation!" + +exit_event = m5.simulate() + +print 'Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause()) -- GitLab