simple-caches.py 1.66 KB
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import m5
from m5.objects import *
from Caches import *

system = System()

system.clk_domain = SrcClockDomain(clock='1GHz', voltage_domain = VoltageDomain())
system.mem_mode = 'timing'
system.mem_ranges = [AddrRange('512MB')]

system.cpu = TimingSimpleCPU()
# system.cpu = MinorCPU()
# system.cpu = DerivO3CPU()

system.cpu.icache = L1ICache()
system.cpu.dcache = L1DCache()

system.cpu.icache.connectCPU(system.cpu.icache_port)
system.cpu.dcache.connectCPU(system.cpu.dcache_port)

system.l2bus = CoherentXBar()
system.cpu.icache.connectBus(system.l2bus)
system.cpu.dcache.connectBus(system.l2bus)

system.l2cache = L2Cache()
system.l2cache.connectCPUSideBus(system.l2bus)

system.membus = SystemXBar()
system.l2chace.connectMemSideBus(system.membus)

# system.cpu.icache_port = system.membus.slave
# system.cpu.dcache_port = system.membus.slave

system.cpu.createInterruptController()

system.system_port = system.membus.slave

system.mem_ctrl = DDR3_1600_x64()
system.mem_ctrl.range = system.mem_ranges[0]
system.mem_ctrl.port = system.membus.master

process = LiveProcess()
process.cmd = ['/home/vagrant/advanced_computer_architecture/exercises/blatt01/exec/hello/hello_world']
system.cpu.workload = process
system.cpu.createThreads()

root = Root(full_system = False, system = system)

m5.instantiate()
exit_event = m5.simulate()

# newprocess = LiveProcess()
# newprocess.cmd = ['/home/vagrant/advanced_computer_architecture/exercises/blatt01/exec/automotive/basicmath/basicmath_small']
# system.cpu.workload = newprocess
# system.cpu.createThreads()


# print "Beginning simulation!"
# exit_event = m5.simulate()

print 'Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause())